Circuit arrangement for capacitive read signal amplification in

Details Circuit arrangement for capacitive read signal amplification in Circuit arrangement for capacitive read signal amplification in

1980-08-21

1983-08-02

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

For complementary information

365154, G11C 700

Patent

active

043970028

ABSTRACT:
After a controlled strong lowering of the word line potential for the purpose of addressing a cell, said potential is immediately recharged simultaneously increasing the potential on the N side of the two PNP injectors of the cell and causing the injector capacitances of the selected storage cells and the bit line capacitances to form a capacitive voltage divider, so that the bit lines connected thereto are recharged to different degrees by the different magnitudes of the injector capacitances. Thus, the differential signal formed on the bit lines is noticeably amplified by the supply of currents of different magnitudes.

REFERENCES:
patent: 3736477 (1973-05-01), Berger et al.
patent: 3816758 (1974-06-01), Berger et al.
patent: 4007451 (1977-02-01), Heuber et al.
patent: 4021786 (1977-05-01), Peterson
patent: 4023148 (1977-05-01), Heuber et al.
patent: 4090255 (1978-05-01), Berger et al.
patent: 4168539 (1979-09-01), Anderson
patent: 4259730 (1981-03-01), Heuber et al.

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