Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-06-07
2011-06-07
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000
Reexamination Certificate
active
07958418
ABSTRACT:
A circuit arrangement may include a scan test input stage having a test input for receiving a test signal, wherein the scan test input stage can be switched in high-impedance state; a data input stage having a data input for receiving a data signal, wherein the data input stage can be switched in high-impedance state. The circuit arrangement may further include a latch coupled to at least one output of the scan test input stage and to at least one output of the data input stage; and a drive circuit, which is configured to generate a pulsed clock signal for the data input stage and a signal for driving the scan test input stage.
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Berthold Joerg
Henzler Stephan
Koppe Siegmar
Pacha Christian
Gaffin Jeffrey A
Infineon - Technologies AG
Lee & Hayes PLLC
Merant Guerrier
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