Circuit and signal encoding method for reducing the number...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique

Reexamination Certificate

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Details

C714S700000, C714S048000, C360S032000

Reexamination Certificate

active

07020834

ABSTRACT:
A Circuit for reducing the number of serial ATA external PHY signals includes: a serializer/deserializer, connected to a storage medium controller through a set of parallel signal transmitting lines and a set of parallel signal receiving lines, so as to convert signals between parallel and serial specifications; a phase locked loop, connected to the serializer/deserializer so as to generate a clock signal required for data signal transmission; at least one pair of transmitter and receiver, each connected to the serializer/deserializer, each transmitter able to transmit the serial data signal from the serializer through a set of serial signal transmitting lines to a serial ATA device, and each receiver able to receive the serial data from the serial ATA device through a set of serial signal receiving lines to the deserializer; and at least one OOB signal detector, each connected to the corresponding receiving lines, so as to detect the out of band signals from the serial ATA device. The Circuit also employs in certain applications a signal encoding approach for reducing the number of serial ATA external PHY signals, wherein an encoder and a decoder are employed to encode control signals and status signals into special data codes transmitted between a serial ATA external PHY and a storage medium controller, so as to minimize the number of interface signals.

REFERENCES:
patent: 5299193 (1994-03-01), Szczepanek
patent: 5953386 (1999-09-01), Anderson
patent: 6397042 (2002-05-01), Prentice et al.
patent: 6650141 (2003-11-01), Agrawal et al.
patent: 6662332 (2003-12-01), Kimmitt

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