Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2001-10-04
2002-08-13
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S189110
Reexamination Certificate
active
06434071
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a memory read operation and, more particularly, to selectively activating feedback devices for local bit lines in a memory.
2. Description of the Related Art
In a memory, there are read bit lines which are often dynamic nodes and must be precharged. The read bit lines have a number of memory cell outputs attached to them. The memory cell outputs can only pull the read bit lines low. Commonly, read bit lines are split into “local” read bit lines to reduce capacitive load and increase data-accessing speed. Therefore, there may be two or more “local” read bit lines in a memory.
Preferably, a p-channel metal-oxide-semiconductor field effect transistor (“MOSFET”) is used to precharge a local read bit line high when a local read bit line reset clock signal (lcl_rbl_rst) is asserted low. After the lcl_rbl_rst clock signal has transitioned to a high state, a feedback device or transistor (also known as a “keeper transistor”) will hold each local read bit line high until the lcl_rbl_rst clock signal transitions to a low state or a memory cell output discharges the local read bit line. Preferably, the feedback device will comprise a p-channel MOSFET smaller in size than the one used for precharging.
Conventionally, the feedback device is driven by an inverter having its input from the local read bit line. Such an inverter generally consists of transistors and thus will add more capacitance to read bit lines. This added capacitance will slow the response time of the local read bit lines, thereby slowing the data-reading process of the memory. Furthermore, the conventional configuration may consume more power than is necessary. This is because the conventional configuration requires an inverter for each feedback device or a local read bit line. For example, if there are two local read bit lines, two inverters are used to drive two feedback devices, each inverter driving one feedback device. Each of the feedback devices is used to hold the local read bit line high. In doing so, the feedback devices “fight” leakage and thus power is consumed. Since the two inverters function independently of each other, one inverter may keep a feedback device on in cases where the output of the feedback device does not affect the output of the entire precharge circuit. In such cases, therefore, having an inverter for each feedback device leads to more power consumption than is necessary.
Therefore, there is a need for an optimized circuit configuration that does not require as much capacitance and/or power as conventionally circuits.
SUMMARY OF THE INVENTION
The present invention provides a precharge circuit configured for reading a data bit from a memory having at least two local bit lines. The precharge circuit comprises a first precharge transistor connectable to a voltage source and a first local bit line of the memory for precharging the first local bit line, when the first precharge transistor is turned on. Additionally, a first keeper transistor is connectable to the voltage source and the first local bit line for keeping the first local bit line precharged, even after the first precharge transistor is turned off.
The precharge circuit further comprises a second precharge transistor connectable to the voltage source and a second local bit line of the memory for precharging the second local bit line, when the second precharge transistor is turned on. A second keeper transistor is also connectable to the voltage source and the second local bit line for keeping the second local bit line precharged, even after the second precharge transistor is turned off. A NAND gate is connectable to the first and second local bit lines for receiving the data bit from the memory, and connected to the first and second keeper transistors for switching the first and second keeper transistors.
Alternatively, a method is provided for reading a data bit from a memory having first and second local bit lines. The method comprises the steps of inputting the first and second local bit lines to a NAND gate, precharging the first and second local bit lines by turning on first and second precharge transistors, respectively. The first and second precharge transistors are connectable to a voltage source and the first and second local bit lines.
The method comprises the additional steps of turning on first and second keeper transistors, keeping the first and second local bit lines precharged by maintaining the first and second keeper transistors turned on, respectively, even after the first and second precharge transistors are turned off, inputting the data bit to the NAND gate via one of the first and second local bit lines, switching the first and second keeper transistors by the NAND gate, outputting an inverted value of the data bit from the NAND gate, when both the first and second precharge transistors are turned off, and obtaining the data bit by inverting the inverted value of the data bit. The first and second keeper transistors are connectable to the voltage source and the first and second local bit lines.
REFERENCES:
patent: 5007023 (1991-04-01), Kim et al.
patent: 6333881 (2001-12-01), Kusunoki et al.
Carr Law Firm, L.L.P.
Carwell Robert M.
Hoang Huan
International Business Machines - Corporation
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