Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1996-02-20
2003-07-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06587978
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is being filed simultaneously with and contains similar material to copending application having Ser. No. 08/196,619, entitled “A CIRCUIT AND METHOD FOR VARYING A PERIOD OF AN INTERNAL CONTROL SIGNAL DURING A TEST MODE.”
This application may also contain similar material to copending U.S. patent application Ser. No. 08/121,813, entitled “A CIRCUIT AND METHOD FOR DISABLING A LOCKOUT FUNCTION,” and to copending U.S. patent application Ser. No. 08/096,643, entitled “SEMICONDUCTOR ARRAY HAVING BUILT-IN TEST CIRCUITRY FOR WAFER LEVEL TESTING.”
FIELD OF THE INVENTION
The invention relates to the testing of electrical devices, and more particularly to an internal test key and internal circuitry for testing an encapsulated DRAM.
BACKGROUND OF THE INVENTION
A dynamic random access memory (DRAM) consists of an arrangement of individual memory cells. Each memory cell comprises a capacitor capable of holding a charge and a field effect transistor, hereinafter referred to as an access transistor, for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Therefore, the memory has two states; often thought of as the true logic state and the complementary logic state. An arrangement of memory cells is called an array. There are two options available in a DRAM memory: a bit of data may be stored in a specific cell in the write mode, or a bit of data may be retrieved from a specific cell in the read mode. The data is transmitted on signal lines, also called digit lines, to and from the Input/Output lines, hereinafter known as I/O lines, through field effect transistors used as switching devices and called decode transistors. For each bit of data stored, its true logic state is available at the I/O lines and its complementary logic state is available at lines designated I/O*. Each cell has two digit lines referred to as digit line pairs.
In order to read from or write to a cell, the particular cell in question must be selected, also called addressed. Typically, the cells are arranged in the array in a configuration of intersecting rows and columns. In previous generations of DRAMs to select a cell an active output from a row decoder selects a wordline appropriate to the given address in response to an active external row address strobe (RAS) signal. In most applications the active RAS signal is low. The active wordline then turns on the cell's access transistor. Next the column decoder activates and selects the desired digit line pair in response to a column address strobe (CAS) signal. For a write operation the active column decoder output activates the decode transistors to pass the data to be written from the I/O lines to the digit line pair. The data is coupled through the access transistor to the memory cells which store the data.
More recent generations of DRAMS have lockout circuits on board that “catch” pulses that are too short and lock out the premature transitions of external signals to the DRAM. For example if the tRAS functional specification, the minimum time that RAS must be active for the DRAM to function normally, is violated the lockout circuit will ignore a transition of the external RAS signal to the inactive state until the DRAM has had time to sense and restore the memory properly. Thus the lockout circuit generates an internal RAS signal having a greater pulse width than the pulse width of the corresponding external RAS signal when the external RAS signal doesn't meet the tRAS functional specification. A similar circuit exists for tRP, the minimum time that RAS must be inactive during precharge. In both cases lockout circuits have made testing of the DRAM more difficult.
The tRAS functional specification as defined above and the tRAS specification typically defined in the DRAM data book should not be confused. In order to meet the data book tRAS specification the DRAM must function normally if the external RAS signal is active for a length of time equal to or greater than the data book tRAS specification.
Before the internal lockout circuits were incorporated into the DRAM circuit the pulse width of the external control signal could be decreased or increased, as the case may be, to stress the DRAM while testing the device. With the advent of internal lockout circuits this is no longer possible since the lockout circuit automatically decreases or increases the pulse width of the external control signal when it fails to meet the functional specification. Thus testing becomes more difficult, especially on encapsulated DRAMs. Instead of failing for a simple test, such as would be the case where the pulse width of an external control signal can be varied, the part fails more complicated tests later in the test flow process.
There exists a need to be able to test, with better guardband, DRAMs having lockout circuitry. The guardband is a region in which the part is capable of operating which lies outside of a region defined by the specifications of the part.
For DRAMS having self-refresh, the internal refresh rate is variable due to process variation, temperature effects, voltage levels, and in some cases elective trimming to attain a particular refresh rate or standby current level. Since the refresh is done internally, it can be estimated but not measured. This makes it impossible to detect whether the part is right on the edge of failing or not.
In order to ensure that you have guardband for the self-refresh mode, there exits a need to find a way to increase the period of the refresh cycle during a test mode. Parts which pass tests when the period of the refresh cycle is increased are not on the edge of failing.
SUMMARY OF THE INVENTION
The invention is a monolithic chip having a timing circuit, a memory circuit, and an electronic test key fabricated on board and is the method of testing the monolithic chip. The timing circuit generates a control signal in response to a timing signal. The electronic test key responds to a test signal and generates a mode signal to control a value of a pulse width of said control signal during normal operation and during a test mode. The memory circuit responds to the control signal during normal operations and during a test mode.
Typically, the electronic test key responds to at least one external test signal to control a circuit test on the part. The electronic test key generates a signal which varies a pulse width of a pulse of an internal control signal in order to stress the part and test with good guardband and margin. The invention is particularly useful in DRAM technologies.
In one embodiment, the invention is an electronic circuit having a lockout circuit and an electronic test key. The lockout circuit generates an internal control signal. During normal operation the lockout circuit responds to an external control signal to generate an internal control signal having a desired pulse width independent of a pulse width of the external control signal. During testing, the electronic test key on the DRAM generates a mode signal which varies the pulse width of the active pulse of the internal control signal to stress the electronic circuit. Circuit tests are then performed to see if the circuit functions correctly when stressed.
The invention ensures that parts which pass the test mode have good guardband and provides good production feedback. For example, lots of DRAMs that have a high row line resistance will be susceptible to a shorter tRP pulse width. The test mode of the invention weeds out parts that are on the verge of failing due to the lock-outs being too “tight”. It will also give feedback as to where lockout delays should be adjusted and if there are defective delay elements in the lockout circuits.
REFERENCES:
patent: 3781683 (1973-12-01), Freed
patent: 3803483 (1974-04-01), McMahon, Jr.
patent: 3832535 (1974-08-01), De Vito
patent: 3849872 (1974-11-01), Hubacher
patent: 4079338 (1978-03-01), Kronlage
patent: 4099722 (1978-07-01), Rodesch et al.
patent: 4139818 (1979-02-01), Schneider
patent: 4
Casper Stephen L.
Merritt Todd A.
Raad George B.
De'cady Albert
Lamarre Guy
Schwegman Lundberg Woessner & Kluth P.A.
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