Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
1999-06-10
2001-05-29
Nelms, David (Department: 2818)
Electronic digital logic circuitry
With test facilitating feature
C326S038000, C326S041000
Reexamination Certificate
active
06239611
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to methods and circuits for testing programmable logic devices, and in particular to methods and circuits for ensuring that programmable logic devices meet zero-hold-time requirements.
BACKGROUND
“Set-up time” and “hold time” describe the timing requirements on the data input of a sequential logic element, such as a flip-flop or register, with respect to a clock input. The set-up and hold times define a window of time during which data must be stable to guarantee predictable performance over a full range of operating conditions and manufacturing tolerances.
FIG. 1
illustrates three clock-to-data timing relationships used to describe the relationships between set-up time, hold time, and a clock edge. Referring to the first example, the set-up time SUT is the length of time that data must be available and stable before the arrival of a clock edge
100
. The hold time HT is the length of time that data to be clocked into the storage element must remain stable after the arrival of clock edge
100
. Positive hold times limit the maximum clock rate of a system. Thus, chip designers and system designers strive to meet zero-hold-time requirements.
The second example in
FIG. 1
illustrates the input and output signals of a flip-flop that meets a zero-hold-time requirement. The data, a logic one at the onset of rising edge
110
, propagates through the selected logic element to raise the output signal OUT to a logic one. The third example illustrates the input and output signals of a flip-flop that fails to meet a zero-hold-time requirement. The data, a logic one at the onset of rising edge
120
, does not initiate the requisite logic one output signal OUT.
IC designs typically guarantee that any individual sequential logic element does not require a positive hold time with respect to the corresponding clock signal. Hold-time requirements between flip-flops or registers on the same chip can be avoided by careful design of the on-chip clock distribution network.
The time required for the output of a sequential storage element to change states in response to a clock is termed the “clock-to-out” delay. If the worst-case clock-skew value is shorter than the sum of the minimum clock-to-out delay plus the minimum signal propagation delays between sequential elements, then there is never any on-chip hold-time problem. It can be difficult, however, to avoid hold-time problems for sequential storage elements that communicate with data sources external to the chip.
Device data inputs will have a positive (non-zero) hold-time requirement if the internal clock distribution delay is longer than the data input delay. This means that the data source, usually another IC driven by the same clock signal, must guarantee to maintain data signals beyond the clock edge. Otherwise, the receiving device might erroneously input the next (incorrect) data instead of the data created by the current clock. This is called a race condition, and can cause fatal system failures.
If the receiving device has a hold time requirement, the data source must guarantee an equivalent minimum value for its clock-to-out delay. Few IC manufacturers are willing to do this, and in the few cases where it is done, the minimum value is typically a token one nanosecond. Any input hold time requirement is, therefore, an invitation to system failure. Clock delays induced by the interconnections between ICs can make matters worse.
FIG. 2
illustrates a conventional programmable input block
200
that addresses potential hold-time problems. (Input block
200
is part of an input/output block on a Xilinx XC4000 FPGA.) Input block
200
includes an input buffer
205
, programmable delay circuit
210
, a sequential storage element
215
, and three programmable multiplexers
220
,
225
, and
230
. A programmable multiplexer
240
can be programmed to insert one or both of delay elements
235
into the incoming data path to compensate for clock delays induced by relatively long signal paths in the clock distribution network. Multiplexer
230
includes both inverting and non-inverting inputs, allowing storage element
215
to clock on either positive or negative clock edges.
FIG. 3
depicts a conventional test configuration
300
for ensuring that a selected sequential storage element on a programmable logic device meets a zero-hold-time requirement. System
300
includes a conventional tester
305
connected to a field-programmable gate array (FPGA)
310
. FPGA
310
is a well-known type of programmable logic device, and might be one of the Spartan™ series of FPGAs available from Xilinx, Inc., of San Jose, Calif. FPGA
310
includes an array of configurable logic blocks
311
, or CLBS, that are programmably interconnected to each other and to programmable input/output blocks
312
(IOBs). This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that define how the CLBs, interconnections, and IOBs are configured. FPGA
310
additionally includes a clock distribution network
313
that can be connected to an external clock source (not shown) via eight global clock buffers
314
located in the four corners of FPGA
310
. Each global clock buffer
314
has a corresponding pass transistor for gating an external clock signal to the input terminal of the respective clock buffer. For example, a pass transistor
315
selectively gates the signal on an input pin
325
through one of clock buffers
314
to clock distribution network
313
. The signal on input pin
325
is additionally available to IOB
312
B.
Clock distribution network
313
can be programmably connected to any of CLBs
311
or IOBs
312
. In the depicted example, clock distribution network
313
connects input pin
325
to an input terminal of IOB
312
A via clock distribution network
313
.
Each programming point, CLB, interconnection line, and IOB introduces some delay into a signal path. The many potential combinations of these and other delay-inducing elements make timing predictions difficult. Testing an FPGA to ensure that all input paths meet a zero-hold-time requirement is therefore very time consuming. There is therefore a need for a faster method of testing for zero-hold-time compliance.
Tester
305
includes a pair of output leads
317
and
320
connected to respective input/output pins
325
and
330
of FPGA
310
. Tester
305
also includes an input line
335
connected to an input/output pin
340
of FPGA
310
. Tester
305
simultaneously applies input signals to pins
325
and
330
and monitors the output signal on line
335
to determine whether the correct data on line
320
clocks into IOB
312
A. An incorrect logic level on line
320
indicates a hold-time violation.
Conventional test configuration
300
can be inaccurate due to the imprecision of tester
305
and the impact of leads
317
and
320
on the measurement. Testers have tolerances that can have a significant impact on some measurements, particularly when the signal propagation delay of interest is short. For example, if tester
305
can be relied upon to produce a signal edge accurate to one nanosecond, then the difference between “simultaneously” developed signals on lines
317
and
320
can only be assumed to be accurate to two nanoseconds.
Parts that are found acceptable by tester
305
but that fail to meet zero-hold-time requirements in customer applications lead to unhappy customers. Thus, IC manufacturers tend to add relatively large margins of error, or “guard bands,” to ensure that their circuits will perform as advertised. If the difference between “simultaneously” developed signals can only be assumed to be accurate to two nanoseconds, for example, then IC manufacturers would typically provide a guard band of at least two-nanoseconds. Unfortunately, this means that manufacturers would not be able to guarantee the highest potential speed performance, which could cost them customers in an industry where speed performance is paramount.
IC manufacturers would like to g
Auduong Gene N.
Behiel Arthur J.
Nelms David
Xilinx , Inc.
Young Edel M.
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