Circuit and method for test mode entry of a semiconductor...

Details Circuit and method for test mode entry of a semiconductor... Circuit and method for test mode entry of a semiconductor...

2007-02-27

2007-02-27

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

11256357

ABSTRACT:
A circuit and method for test mode entry of a semiconductor memory device are provided. In a method of entering a semiconductor memory device into a test mode, an internal clock is generated in response to an external clock when a first condition is satisfied. An address combination signal is generated based on a first address combination and the internal clock. The semiconductor memory device is entered into the test mode using the internal clock and the address combination signal.

REFERENCES:
patent: 6353565 (2002-03-01), Ito
patent: 6400623 (2002-06-01), Ohno
patent: 7035154 (2006-04-01), Takahashi et al.
patent: 2000-215695 (2000-08-01), None
patent: 1020040003562 (2004-01-01), None

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