Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-06-07
2005-06-07
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S723000, C365S189011
Reexamination Certificate
active
06904552
ABSTRACT:
A preferred exemplary embodiment of the current invention concerns a memory testing process, wherein circuitry is provided on a chip to allow on-chip comparison of stored data and expected data. The on-chip comparison allows the tester to transmit in a parallel manner the expected data to a plurality of chips. In a preferred embodiment, at most one address—and only the column address—corresponding to a failed memory cell is stored in an on-chip register at one time, with each earlier failed addresses being cleared from the register in favor of a subsequent failed address. Another bit—the “fail flag” bit—is stored in the register to indicate that a failure has occurred. If the fail flag is present in a chip, that chip is repaired by electrically associating the column address with redundant memory cells rather than the original memory cells. Subsequently, the chip's register may be cleared and testing may continue. It is preferred that the register and related logic circuitry be configured to avoid storing an address that is already associated with a redundant cell, even though that redundant cell has failed.
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Micron Technology, Inc.; “Synchronous DRAM” Data Sheets; 128Mb: x32 SDRAM, 128Mb: x32 DRAM, 128MbSDRAMx32, p65—Rev. Sep. 2000, pp.1-52.
Brantley Charles
Micron Technolgy, Inc.
Tu Christine T.
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