Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1997-11-04
2000-08-29
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714720, G11C 2900
Patent
active
061123226
ABSTRACT:
A circuit and method are provided for stress-testing EEPROMS by incrementally selecting and deselecting word lines. The circuit of the invention comprises a memory cell array, a set of decoders for decoding a memory address bus and controlling word lines for the memory cell array, a control circuit, and a shift register driven by the control circuit. Each bit of the shift register has the capability of overriding a group of one or more of the decoders. When the initiation signal is received by the control circuit, a state control bit is set high and is clocked through the shift register. The high bit overrides successive groups of decoders as it is shifted through the shift register, until all word lines in the memory cell array are selected. After the stress test has been performed, the state control bit is returned to zero and is cycled through the shift register on successive clock cycles, incrementally deselecting groups of word lines until all word lines are deselected.
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"The Programmable Logic Data Book", 1996, p. 4-28, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Ahrens Michael G.
McGibney Phillip H.
Cady Albert De
Cartier Lois D.
Casesy, Esq. Michael R.
Ton David
Xilinx , Inc.
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