Circuit and method for retaining data in DRAM in a portable elec

Details Circuit and method for retaining data in DRAM in a portable elec Circuit and method for retaining data in DRAM in a portable elec

1997-10-27

1998-10-20

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, 395427, G11C 700

Patent

active

058257063

ABSTRACT:
When an external reset signal EXRST is asserted received by a reset unit (6), it is synchronised with an internal clock to produce an internal reset signal INRST, which is applied to a CPU (4) and other modules in the circuit to reset them. While the internal reset signal INRST is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller (7) for refreshing data in DRAM (3) is increased. Then, when the external reset signal EXRST is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller (7) so that it is reset. The CPU, being already reset, can then quickly reconfigure the DRAM controller and re-enable it to resume refreshing the DRAM (4), thus maintaining the data in the DRAM.

REFERENCES:
patent: 5321661 (1994-06-01), Iwakiri et al.
patent: 5402384 (1995-03-01), Fujisawa
patent: 5453959 (1995-09-01), Sakuta et al.
patent: 5477491 (1995-12-01), Shirai
patent: 5537564 (1996-07-01), Hazanchuk

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