Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-30
2001-12-11
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S255000, C257S256000, C257S257000, C257S258000, C257S261000, C257S263000
Reexamination Certificate
active
06329692
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to circuits, and more particularly, to a circuit and method for reducing parasitic bipolar effects during electrostatic discharges.
BACKGROUND OF THE INVENTION
An integrated circuit can be damaged when subjected to a voltage that is higher than the design voltage of the integrated circuit. Electrostatic discharge (“ESD”), originating from such sources as a mechanical chip carrier, a plastic chip storage device, or even a human being can generate a voltage that is many times greater than the design voltage of the integrated circuit. For example, the typical human body can supply an electrostatic discharge of up to 4 kilovolts. For integrated circuits that operate at voltages of less than, for example, 5 volts, an electrostatic discharge of such proportions can be devastating.
In order to protect the internal circuitry from high voltage, or ESD, events, protection circuits are utilized, generally between the internal circuitry and the input/output (“I/O”) pins of the integrated circuit. One mechanism that can cause circuit failures during ESD events is a phenomenon known as “bipolar snapback”.
FIG. 1
illustrates, in partial schematic diagram form and partial cross-sectional view, an N-channel metal-oxide semiconductor (MOS) transistor and an inherent parasitic bipolar transistor in accordance with the prior art. As
FIG. 1
illustrates, an NPN bipolar device is formed in the p substrate having an emitter coupled to the source, a collector coupled to the drain, and a base coupled to the substrate of an N-channel MOS transistor. In
FIG. 1
, the substrate tie and the source are illustrated coupled to ground with the drain coupled to an I/O pad. The I/O pad is shown receiving a positive ESD event.
During bipolar snapback, the parasitic bipolar device formed by an n+ diffusion coupled to the bondpad (collector) and an n+ diffusion coupled to ground (emitter), can conduct large amounts of ESD discharge current by means of a self-biased mechanism through the inherent substrate resistance labeled “Rsub”. The self-biasing results from avalanche-breakdown at the collector/base (i.e. n+ pad to p-substrate) diffusion where avalanche-generated electron-hole pairs are created. The avalanche-generation source is shown schematically as current source I
GEN
in
FIG. 1
, which represents substrate (hole) current. The holes generated from this effect migrate towards the substrate tie through the inherent substrate resistance, thereby producing a local elevation in the substrate potential near the transistor. Once this potential exceeds roughly 0.7V, it is sufficient to forward bias the base-emitter junction (i.e. n+ to p-substrate) of the parasitic device, thereby turning the device on. The drain-to-source voltage and drain current point at which parasitic bipolar action first occurs is called (V
T
1
, I
T
1
), where I
T
1
is the current which is flowing due to the avalanche-generation at the drain/substrate junction. Usually, the bipolar device inherently contained in the N-channel MOS device of, for example, an output buffer is the most susceptible to snapback. This parasitic device is frequently the point of failure in a circuit subjected to an ESD event.
One well-known solution to alleviate this parasitic bipolar problem is to add a ballast resistor connected between the drain of the N-channel MOS transistor and an output pin. This technique helps ensure some added measure of ESD protection in the event of bipolar conduction in the circuit by equally distributing any discharge current through the NMOS transistor (or several fingers forming a single NMOS transistor). The ballast resistor is added to ensure that the failure point at another collector-to-emitter voltage V
T
2
, is greater than the collector-to-emitter voltage, V
T
1
, where the current begins to flow in the parasitic bipolar transistor. The relationship between V
T
1
and V
T
2
is illustrated in FIG.
2
.
FIG. 2
illustrates a diagram of drain current versus drain voltage of the N-channel transistor of FIG.
1
.
FIG. 2
shows two curves. One curve illustrates drain current versus drain-to-source voltage for a typical non-salicided technology and the other curve illustrates drain current versus drain-to-source voltage for a typical salicided technology. When several NMOS transistors (or several fingers forming a single NMOS transistor) act as a parasitic bipolar device, such a device relies upon the “snap-back” current-voltage characteristics of the inherent parasitic bipolar transistor. As stated above, a current begins to flow through the bipolar transistor at a certain collector-to-emitter voltage, V
T
1
. Thereafter the collector-to-emitter voltage decreases as the current increases, “snapping back” from V
T
1
. As drain voltage increases, the trend reverses, causing the collector-to-emitter voltage to rise as the current also rises. Eventually, the bipolar transistor fails at another particular collector-to-emitter voltage V
T
2
. In a typical non-salicided technology, V
T
2
is usually greater than V
T
1
since the on-resistance exhibited by the transistor is quite high (i.e. the slope of the line in
FIG. 2
is less steep). In a typical salicided technology, V
T
2
is usually less than V
T
1
, since the salicided source/drain diffusions act to lower the effective series resistance of the device (i.e. the slope of the line in
FIG. 2
is more steep). In either technology, V
T
2
can be controlled to be greater than V
T
1
by adding series resistance in the form of a ballast resistor. This guarantees that the first NMOS transistor (or finger of the NMOS transistor) does not break down at a voltage less than the voltage at which the second NMOS transistor turns on. This in turn guarantees that the failure current of the complete device is the sum total of its individual components rather than that of the first segment which snaps-back. The failure current is the second breakdown current, I
T
2
, shown in FIG.
2
. The value of I
T
2
must not be exceeded during an ESD event or else permanent damage will result in the device. Thus, the motivation for adding ballast resistance is to maximize the total amount of I
T
2
available from a given transistor. In general, I
T
2
depends on specific fabrication parameters of a particular technology, and varies from technology to technology.
The general trend with semiconductor technology scaling has been a reduction in I
T
2
for each new generation of technology. This is due to several factors such as the use of shallow, salicided source/drain junctions and the use of epitaxial layer on heavily doped p+ substrates. In addition to promoting poor width-scaling in multi-finger devices, the salicide layer also consumes a significant portion of the junction depth which is also known to reduce second breakdown failure current thresholds (I
T
2
). Epitaxial layer on heavily doped p+ substrates (epi-substrates), are needed in advanced technologies to inhibit the well known latch-up effect. Epi-substrates exhibit a very low substrate resistance, which allows the substrate potential to be closely coupled to ground all over the chip. While this is desirable for avoiding latch-up, it severely impedes parasitic bipolar action since it becomes difficult to uniformly initiate and sustain bipolar action.
REFERENCES:
patent: 5019888 (1991-05-01), Scott et al.
patent: 5021853 (1991-06-01), Mistry
patent: 5157573 (1992-10-01), Lee et al.
patent: 5225702 (1993-07-01), Chatterjee
patent: 5440162 (1995-08-01), Worley et al.
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5903419 (1999-05-01), Smith
“Substrate Triggering and Salicide Effects on ESD Performances and Protection Circuit Design in Deep Submicron CMOS Process,” Amerasekera, et al; IEDM 95; pp. 575-550.
“A Substrate Triggered Lateral Bipolar Circuit for High Voltage Tolerant ESD Protection Applications,” Smith.
“EOS/ESD Analysis of High-Density Logic Chips,” Ramaswamy, et al; EOS/ESD Symposium 96; pp. 286-290.
“Analysis of Snubber-Clamped Diode-String Mi
Hill Daniel D.
Motorola Inc.
Wojciechowicz Edward
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