Circuit and method for modulo address generation with reduced ci

Details Circuit and method for modulo address generation with reduced ci Circuit and method for modulo address generation with reduced ci

1997-08-29

2000-04-18

Cabeca, John W.

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

711218, 711219, 711220, G06F 1206

Patent

active

060527684

ABSTRACT:
The present invention relates to a modulo address generator and method thereof. The apparatus includes an adder which adds a current address value and an address increment value to generate an incremented address value. Also included is an adder/subtracter circuit which adds a data region size value to the incremented address value when the sign bit of the address increment value is negative and subtracts the data region size value from the incremented address value when the sign bit is positive in order to generate a revised address value. An output selection circuit selects either the incremented address value, when the sign bit is negative, or the revised address value, when the sign bit is positive, for comparison to a minimum address of the data region in order to generate a comparison result value. When the selected address value is greater than or equal to the minimum address, the comparison result value is set to a negative value and combined with the sign bit to select one of the incremented address value and the revised address value for output as the next address value.

REFERENCES:
patent: 4800524 (1989-01-01), Roesgen
patent: 4833602 (1989-05-01), Levy et al.
patent: 5659700 (1997-08-01), Chen et al.
patent: 5790443 (1998-08-01), Shen et al.

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