Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-08-31
2002-08-20
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S166000
Reexamination Certificate
active
06438710
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to various microprocessor based applications and, more particularly, to a reset circuit for improving memory integrity suitable for use in an automatic call distributor.
BACKGROUND OF THE INVENTION
An automatic call distributor (ACD) is one example of a microprocessor based application. A typical ACD includes a central processing unit in conjunction with a main memory. The ACD functions to selectively interconnect telephonic calls received from external telephones of an external telephonic network with a number of internal telephonic units. An ACD may include a number of microprocessors which store data in electronic memory.
As will be apparent to one of ordinary skill in the relevant art, one requirement of such an ACD system is that data stored in memory must be maintained when the microprocessor is reset. Resets can occur in a number of different ways such as, for example, a deliberate reset which is caused by pressing a reset button, an automatic reset when the electronic circuitry itself senses a fault and needs to reset itself, or when a system administrator requests that the system reset itself.
When a reset signal is received, it is likely that the microprocessor is completing a write cycle to electronic memory such as, for example, Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM) memory. Thus, if the microprocessor is forced to reset without completing the write cycle to electronic memory, data in electronic memory may be corrupted. Thus, after the microprocessor is reset, the electronic memory may need to be verified and reloaded, which leads to increased time to bring the system to a functioning level.
Currently, a microprocessor of a system such as an ACD may be reset asynchronously, i.e. at any time that an external reset signal is sent to the microprocessor. If the microprocessor is currently executing a write to memory or has pending writes to memory, then these tasks are lost when the microprocessor is reset. For example, if the microprocessor is manually reset while memory is being written, then the write cycle in progress is aborted and the data is not written to memory. By asynchronously resetting the microprocessor, memory integrity is lost. Moreover, corrupt data in memory may cause undesirable behavior and/or system failure.
While the existing method of resetting a microprocessor of a system such as an ACD is relatively satisfactory, it causes memory to become corrupted in a number of different circumstances. As a consequence, system failure may occur or it may take a long time to validate or reload memory contents after a reset. Delays of this type cause significant economic harm to the operators of systems such as ACDs whose livelihood directly depends upon the rapid and proper routing of calls. Accordingly, a need exists for a better circuit and method for guaranteeing memory integrity in a microprocessor based system such as an ACD.
BRIEF SUMMARY OF THE INVENTION
In one embodiment, the present invention provides a circuit for improving memory integrity during reset. One embodiment of the circuit comprises, for example, a reset input to receive external reset signals, a bus monitor which monitors bus activity and generates a bus access signal when the bus is idle, and a reset generator responsive to the bus access signal to generate an internal reset signal in response to the external reset signal when the bus is idle.
In one specific embodiment of the invention, a reset controller comprises a reset signal generating means for generating the internal reset signal in response to the external reset signal being received and the bus access signal being received.
In another embodiment of the invention, the circuit further comprises a variable timer which generates an internal reset signal after waiting an interval of time which is appropriate for the recent bus activity. If a history of recent bus activity shows that many write cycles have taken place, then this allows, for example, an internal reset signal to be generated after waiting an interval of time appropriate for a write cycle to complete.
In another embodiment of the invention, the circuit further comprises a back-stop timer which automatically generates an internal reset signal after a predetermined interval of time even if the bus access signal indicates that the bus is busy. This allows, for example, a forced reset of the microprocessor when it has been in a bus cycle for a long time.
In one specific embodiment of the invention, the circuit is incorporated in a microprocessor based ACD wherein a reset controller is coupled to an input of the microprocessor to reset the microprocessor when an external reset signal is received by the reset controller. In this example, the external reset signal can be generated by a user of the ACD. Alternatively, for example, the external reset signal can be generated by other circuitry within the ACD.
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Junichi Hiramatsu, Input/Output control device provided with memory protecting function, Nov. 29, 1984, JPAB, JP359210598A, 1-1.
Delong Steven T.
Walsh James P.
Iqbal Nadeem
Rockwell Electronic Commerce Corp.
Welsh & Katz Ltd.
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