Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-03-07
2001-09-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S233100
Reexamination Certificate
active
06292403
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to the field of semiconductor and/or integrated circuit devices, particularly to a random access memory and process for writing to and reading from the same, and more particularly to a circuit and method for implementing single-cycle read/write operation(s) in a random access memory (RAM).
OBJECTS OF THE INVENTION
The primary object of the invention is to provide a circuit and method that enables reading from and writing to a random access memory in the same clock cycle.
Another object of the invention is to provide a circuit and method that enables reading from and writing to a random access memory in the same clock cycle, using a single read/write address bus or separate read and write address busses.
A further object of the invention is to provide a circuit that latches a new address on each edge, transition or level of a periodic and/or control signal.
A further object of the invention is to provide a random access memory that increases data throughput.
Still yet another object of the invention is to provide such a circuit and/or random access memory that reduces the chip area dedicated to transmitting and/or storing address information.
An even further object of the invention is to provide a random access memory and method of operating the same in which read and write operations may be executed in the same clock cycle.
Yet further objects of the invention include providing such a random access memory and method of operating the same in which fully random addresses may be employed, in which successive and/or asserted addresses may be completely unrelated, and/or in which no restrictions are placed on successive and/or asserted addresses.
Another object of the invention is to provide such a random access memory and method of operating the same in which the same address may be used to read from and write to the memory in the same clock cycle.
A further object of the invention is to provide such a random access memory and method of operating the same in which a periodic signal (e.g., a clock) is the only control-type signal essential to operability.
Other objects and advantages of the present invention will become apparent from the following description, taken in connection with the accompanying drawings, wherein, by way of illustration and example, embodiments of the present invention are disclosed.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising an address bus providing random addresses for a random access memory array, and a register configured to store or receive (i) a first random address from the address bus to the random access memory array directly or indirectly in response to a first periodic signal transition and (ii) a second random address from the address bus to the random access memory array directly or indirectly in response to a second periodic signal transition, wherein the second periodic signal transition occurs in the same periodic signal cycle as, and preferably is complementary to, the first periodic signal transition.
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Lovett Simon J.
Pancholy Ashish
Phelan Cathal G.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nelms David
Tran M.
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