Circuit and method for generating a local clock signal...

Details Circuit and method for generating a local clock signal... Circuit and method for generating a local clock signal...

2006-04-11

2006-04-11

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000, C327S149000

Reexamination Certificate

active

07028206

ABSTRACT:
A delay locked loop for generating a replica clock signal synchronized to an externally generated clock signal comprises a succession of separately controlled delay lines. Each of the delay lines has different delay resolution.

REFERENCES:
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patent: 5969551 (1999-10-01), Fujioka
patent: 6229363 (2001-05-01), Eto et al.
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patent: 6480047 (2002-11-01), Abdel-Maguid et al.
patent: 6728163 (2004-04-01), Gomm et al.
patent: 2000347765 (2000-12-01), None
Moon et al, An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance, Mar. 2000, IEEE, Vo. 35, No. 3, pp. 377-384.

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