Static information storage and retrieval – Read/write circuit – Testing
Utility Patent
1999-05-24
2001-01-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S203000, C365S189110, C365S189090
Utility Patent
active
06169694
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques for testing initial reliability of semiconductor devices, and more particularly, to a circuit and method for conducting a fully on-chip wafer level burn-in test which are adapted to generate, in a chip, a stress screen voltage required for a wafer burn-in test, based on an externally supplied voltage and an external control signal, namely, a wafer burn-in signal, thereby being capable of conducting a wafer burn-in test.
2. Description of the Related Art
For semiconductor devices such as DRAMs, a screening test is generally conducted in order to screen out those having poor quality prior to the practical use thereof. For such a screening test, a burn-in test is mainly used which is to test the reliability of DRAMs under the conditions of using an elevated temperature and an elevated voltage.
In such a burn-in test, DRAMs are operated under severe conditions involving an elevated temperature and an elevated voltage so that they exhibit potential failures thereof within a reduced period of time.
To this end, desired parts of a chip should be appropriately stressed, that is, subjected to accelerated stress. In the case of a DRAM using an internal power supply voltage, such a burn-in test is also required. In this case, however, an internal power supply circuit included in such a DRAM should control its internal power supply voltage during a burn-in test in order to prevent the internal circuit of the DRAM from being over-stressed. In other words, the internal power supply circuit should operate to apply stress for only screening to the internal circuit of the DRAM.
A burn-in test may be conducted by varying an external clock signal to be applied to a DRAM to be tested by the user to inform a burn-in test mode of the DRAM, thereby controlling the DRAM to operate in the burn-in test mode. However, a more convenient method is to simply increase an external voltage, to be applied to the DRAM, to a desired level or higher, thereby automatically switching the operation mode of the DRAM to the burn-in test mode.
Meanwhile, for such a burn-in test, the internal power supply voltage, V
INT
, and external application voltage, V
EXT
, should meet the following conditions:
1) The entire circuit should exhibit a constant voltage increase ratio.
That is, it is necessary to increase the voltages V
INT
and V
EXT
, which are applied to circuits on the chip in a normal operation mode at a constant ratio for the entire circuit in a burn-in test mode.
In this regard, the circuits using the external application voltage VEXT and the circuits using the internal power supply voltage VINT should exhibit the same voltage increase ratio in the burn-in test mode, that is, they should use burn-in test voltages increased from those in the normal operation mode by the same voltage increase ratio, respectively.
This condition may be expressed by the following equation:
V
INTB
V
INTN
=
V
EXTB
V
EXTN
=
k
1
=
k
2
2) An appropriate static voltage range should be ensured in a normal operation mode.
That is, since DRAMs are configured to operate normally even in the case of a variation in an external rated voltage, the internal power supply voltage should be constant within the external rated voltage range.
This condition may be expressed by the following equation:
V
INT
=V
INTN
(0.9 V
EXTN
≦V
EXT
≦1.1 V
EXTN
)
In conventional semiconductor devices, a stress screen voltage from the outside should be applied to a die in order to screen failures of initial reliability occurring after a burn-in test.
Where an excessively high external voltage is applied to the die, failures may occur due to such an unstable external voltage. Such failures may result in a failure of the burn-in test.
As a result, there is a waste of time and costs consumed to prepare other wafers for a burn-in test.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the invention is to provide a circuit and a method for conducting a fully on-chip wafer level burn-in test which are adapted to generate, in a chip, a stress screen voltage required for a wafer burn-in test, based on an externally supplied voltage and an external control signal, namely a wafer burn-in signal, thereby being capable of conducting a wafer burn-in test.
In accordance with one aspect, the present invention provides a circuit for conducting a fully on-chip wafer level burn-in test for a chip, comprising: a high voltage generating unit for receiving an external power supply voltage and generating a high voltage for gate oxide film failure screening for a cell in response to the received external power supply voltage; a pad on-chip unit for detecting a wafer burn-in signal and generating a wafer burn-in test mode entry signal upon detecting the wafer burn-in signal; a bit line pre-charge voltage generating unit for generating a bit line pre-charge voltage for the gate oxide film failure screening for the cell in response to the wafer burn-in test mode entry signal output from the pad on-chip unit; and a cell plate voltage generating unit for generating a cell plate voltage for capacitor failure screening for the cell in response to the wafer burn-in test mode entry signal.
In accordance with another aspect, the present invention provides a method for conducting a fully on-chip wafer level burn-in test for a chip, comprising the steps of: (a) receiving an external power supply voltage and generating a high voltage for gate oxide film failure screening for a cell in response to the received external power supply voltage; (b) detecting a wafer burn-in signal and generating a wafer burn-in test mode entry signal upon detecting the wafer burn-in signal; (c) generating a bit line pre-charge voltage for the gate oxide film failure screening for the cell in response to the wafer burn-in test mode entry signal; and (d) generating a cell plate voltage for capacitor failure screening for the cell in response to the wafer burn-in test mode entry signal.
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Kim Young Hee
Nam Young June
Hoang Huan
Hyundai Electronics Industries Co.
Nath Gary M.
Nath & Associates PLLC
Novick Harold L.
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