Circuit and method for controlling write recovery time in...

Static information storage and retrieval – Read/write circuit – Signals

Reexamination Certificate

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C365S233100

Reexamination Certificate

active

07495973

ABSTRACT:
A circuit and a method for controlling a write recovery time (tWR) in a semiconductor memory device are disclosed. The method according to one embodiment of the present invention includes receiving an automatic precharge write command, and generating a tWR control signal, which is delayed from a point in time when the automatic precharge write command is received to a point in time when a last data segment is written in the semiconductor memory device. Therefore, power consumption and clock noise may be reduced since an operation of a counter in the circuit for controlling the tWR may be minimized after a point in time when the last data is written.

REFERENCES:
patent: 6185141 (2001-02-01), Hoshita et al.
patent: 6356494 (2002-03-01), Jang et al.
patent: 6434082 (2002-08-01), Hovis et al.
patent: 7263013 (2007-08-01), Kim
patent: 2002/0105635 (2002-08-01), Koshikawa
patent: 2003/0185075 (2003-10-01), Park et al.
patent: 2005/0099837 (2005-05-01), Im et al.
patent: 2000-207883 (2000-07-01), None
patent: 2003-0088956 (2003-11-01), None
patent: 2005-0041580 (2005-05-01), None
patent: 10-0503850 (2005-07-01), None
patent: 10-0533696 (2005-11-01), None
English language abstract of Korean Publication No. 2003-0088956, Nov. 21, 2003.
English language abstract of Korean Publication No. 2005-0041580, May 4, 2005.
English language abstract of Korean Publication No. 10-0503850, Jul. 18, 2005.
English language abstract of Korean Publication No. 10-0533696, Nov. 29, 2005.
English language abstract of Japanese Publication No. 2000-207883, Jul. 28, 2000.

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