Circuit and method for controlling slew rate of data output...

Details Circuit and method for controlling slew rate of data output... Circuit and method for controlling slew rate of data output...

2008-12-29

2010-10-26

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S185230, C365S230060, C365S191000

Reexamination Certificate

active

07821847

ABSTRACT:
A data output circuit of a semiconductor memory device includes at least two data output pads disposed adjacent to each other, a driver unit configured to output a first data by driving a first pad among the data output pads, and a control unit configured to determine whether a phase of the first data is equal to a phase of adjacent data outputted through second pad adjacent to the first pad, and control a slew rate of the driver unit according to the determination result.

REFERENCES:
patent: 2007/0042722 (2007-02-01), Kim
patent: 2007/0205811 (2007-09-01), Nguyen
patent: 2008/0278208 (2008-11-01), Jung
patent: 2008/0284464 (2008-11-01), Bucossi et al.
patent: 1020000003736 (2000-01-01), None
patent: 1020060075398 (2006-07-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Jul. 29, 2009 with an English Translation.

Affiliated with

Also associated with

Rating

Circuit and method for controlling slew rate of data output... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for controlling slew rate of data output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for controlling slew rate of data output... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4158488