Circuit and method for controlling precharge in...

Static information storage and retrieval – Read/write circuit – Precharge

Reexamination Certificate

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C365S230060, C365S233100

Reexamination Certificate

active

08040747

ABSTRACT:
A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal, a burst end signal, and a read write mode signal; a write clock driver configured to drive the internal clock signal and generate a write burst clock signal in response to the read write mode signal and a data input off signal; a write precharge control unit configured to generate a write auto precharge signal in response to the write burst clock signal, the burst end signal, a write latency signal, and a write address combination signal; and a precharge signal generation unit configured to combine the read and write auto precharge signals and generate an auto precharge signal.

REFERENCES:
patent: 5748560 (1998-05-01), Sawada
patent: 5828612 (1998-10-01), Yu et al.
patent: 6337832 (2002-01-01), Ooishi et al.
patent: 6343040 (2002-01-01), Bae
patent: 7057950 (2006-06-01), Lee
patent: 7057951 (2006-06-01), Im et al.
patent: 7355912 (2008-04-01), Park et al.
patent: 7609584 (2009-10-01), Kim et al.
patent: 2008/0205175 (2008-08-01), Park et al.
patent: 10-302475 (1998-11-01), None
patent: 2007-141439 (2007-06-01), None

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