Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-12-07
2003-02-11
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S194000, C365S233100
Reexamination Certificate
active
06519188
ABSTRACT:
BACKGROUND
1. Field of the Invention
The inventions described in this patent document generally relate to circuits and methods for controlling buffers in a semiconductor memory device. More particularly they relate to circuits and methods for controlling a data input buffer and a data strobe buffer in response to internal rising and falling clock signals generated synchronously in response to an external clock signal.
2. General Background and Related Art
A data input buffer usually detects data input from an external source, and holds the external sourced data until it is stored in a memory cell. However, because the data input buffer is enabled in response to an internal clock signal, which is triggered by an external clock signal, it can be enabled later than when input data is inputted into the data input buffer.
FIG. 1
(Prior Art) is a block diagram of a conventional buffer control circuit for a semiconductor memory device. The buffer control circuit comprises an internal clock signal generator
10
, a buffer controller
20
, a plurality of data input buffers
30
, and a plurality of data strobe buffers
40
. The internal clock signal generator
10
generates an internal clock signal CLKP
4
in response to an external clock signal EXT_CLK . The buffer controller
20
receives a write standby signal WT_STDBY, a write operation enable signal WTRZT (it is at high level during a write operation, and is at low level during a read operation), and a burst operation signal YBST, and then generates a buffer control signal ENDINDS. The write operation enable signal WTRZT and the write standby signal WT_STDBY are generated in response to a write command signal output from a command decoder (not shown). The plurality of data input buffers
30
and the plurality of data strobe buffers
40
are enabled or disabled in response to the buffer control signal ENDINDS.
The
FIG. 1
(Prior Art) arrangement operates as shown in
FIG. 2
(Prior Art) which is a timing diagram. The internal clock signal CLKP
4
is triggered by the external clock signal EXT_CLK. The write operation enable signal WTRZT and the write standby signal WT_STDBY are enabled at high level in response to the internal clock signal CLKP
4
. The buffer control signal ENDINS is enabled at high level in response to the write standby signal WT_STDBY, and then is disabled at low level when the burst operation signal YBST is at low level.
In the conventional buffer control circuit, because the input data DI in inputted into DRAM synchronously in response to a data strobe signal DS delayed by 0.75*tck to 1.25*tck (tck=one period of time of the external clock EXT_CLK), it is more quickly inputted into the DRAM as the period of the external clock EXT_CLK (=tck) gets shorter. The data strobe signal DS is generated synchronously in response to the external clock signal EXT_CLK.
On the other hand, because the buffer control signal ENDINDS is generated in response to the write operation enable signal WTRZT and the write standby signal WT_STDBY which are enabled at high level synchronously in response to the internal clock signal CLK
4
, it can be enabled later than the input data DI inputted synchronously in response to the external clock signal EXT_CLK. As a result, it difficult to realize high-speed operation of a semiconductor memory device.
SUMMARY
Accordingly, this patent document describes inventions including circuits and methods for generating a buffer control signal synchronously in response to internal rising and falling clock signals synchronized with an external clock signal, and operating data input buffers and data strobe buffers in response to the buffer control signal, thereby enabling the data input buffers and data strobe buffers before the input data is inputted thereinto, and achieving a stable high speed operation in a semiconductor memory device.
The arrangements and methods described herein minimize unnecessary power consumption in the high-speed operation by operating the data input buffers only at a write operation region.
Among the various inventions described herein there is described a buffer control circuit for a semiconductor memory device. The buffer control circuit includes a first internal falling clock signal generator for generating a first internal falling clock signal from an external clock signal, and a first internal rising clock signal generator for generating a first internal rising clock signal from the external clock signal. A buffer controller generates a buffer control signal in response to the first and second falling and rising clock signals. A plurality of data input buffers and a plurality of data strobe buffers are enabled or disabled in accordance with the buffer control signal.
There is described a method for controlling a plurality of data input buffers and a plurality of data strobe buffers in a semiconductor memory device. The method includes: generating a first internal falling clock signal and a first internal rising clock signal synchronized with an external clock signal; generating a buffer control signal in response to the first internal rising clock signal, the first internal falling clock signal, and a write standby signal; and enabling or disabling the plurality of data input buffers and the plurality of data strobe buffers in accordance with the buffer control signal.
The foregoing is merely exemplary. Additional features and advantages of the inventions will be more fully appreciated in light of the detailed description, read in conjunction with the accompanying drawings.
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Ryoo Ki Hyung
Yoon Young Jin
Hynix / Semiconductor Inc.
Phan Trong
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