Circuit and method for configuring CAM array margin test and...

Details Circuit and method for configuring CAM array margin test and... Circuit and method for configuring CAM array margin test and...

2007-08-07

2007-08-07

Ton, David (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Testing of error-check system

C714S733000

Reexamination Certificate

active

10626728

ABSTRACT:
A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying various loads to the matchline and/or the discharge line, the match detection circuit demonstrates whether it can overcome the applied loads.

REFERENCES:
patent: 4114010 (1978-09-01), Lewis
patent: 4680760 (1987-07-01), Giles et al.
patent: 6125049 (2000-09-01), Nataraj
patent: 6320777 (2001-11-01), Lines et al.
patent: 6523145 (2003-02-01), Ngo et al.
patent: 6618279 (2003-09-01), Towler et al.
patent: 6697275 (2004-02-01), Sywyk et al.
patent: 6697277 (2004-02-01), Towler et al.
patent: 6867990 (2005-03-01), Regev et al.
patent: 6990001 (2006-01-01), Ma et al.
patent: 2003/0026148 (2003-02-01), Clark et al.

Affiliated with

Also associated with

Rating

Circuit and method for configuring CAM array margin test and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Circuit and method for configuring CAM array margin test and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for configuring CAM array margin test and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3894389