Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2000-03-02
2001-12-11
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S189050, C365S203000, C326S088000
Reexamination Certificate
active
06330196
ABSTRACT:
TECHNICAL FIELD
The invention relates generally to integrated circuit memory devices, and more particularly, to an apparatus and method for driving an output data signal at a high data transfer rate.
BACKGROUND OF THE INVENTION
Conventional computer systems include a processor coupled to a variety of memory devices, including read-only memories (“ROMs”) that traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a packetized memory device known as a SLDRAM memory device. In the SLDRAM architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SLDRAM memory devices receive command packets that include both control and address information. The SLDRAM memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
In order for system memory devices to provide data at data transfer rates comparable to the processing speed, the system memory devices require a data output buffer that can provide data at the required slew-rates and drive capabilities demanded by the computer system. Conventional data output buffers attempt to satisfy this demand with an output driver circuit having both NMOS pull-up and pull-down transistors. The advantages of using an NMOS pull-up transistor in an output driver, rather than a PMOS pull-up transistor, are smaller size, faster switching times, less susceptibility to latch-up, and greater resistance to damage caused by electrostatic discharge.
Shown in
FIG. 1
is a conventional output driver circuit
10
having both an NMOS pull-up transistor and pull-down transistor. In operation, when the output driver
10
receives a high input data signal DR, an inverter
14
produces a low pull-down signal PD to switch OFF an NMOS pull-down transistor
16
, and a conventional boot circuit
18
is activated to generate a high pull-up signal PU that turns ON an NMOS pull-up transistor
20
. The NMOS pull-up transistor
20
couples an output terminal
24
to a supply terminal providing a VCCQ voltage in order to generate a high data output signal DQ. The boot circuit
18
is required to drive the gate terminal of the NMOS pull-up transistor
20
because unless the PU signal applied to the gate of the NMOS pull-up transistor
20
exceeds the VCCQ voltage by at least one threshold voltage of the NMOS pull-up transistor
20
, the output level of the high DQ signal will be diminished by one threshold voltage of the NMOS pull-up transistor
20
. When the output driver
10
receives a low DR signal, the boot circuit
18
is deactivated to turn OFF the NMOS pull-up transistor
20
and the inverter
14
produces a high PD signal to turn ON the NMOS pull-down transistor
16
. The NMOS pull-down transistor
16
couples the output terminal
24
to a ground terminal in order to generate a low DQ signal.
A conventional boot circuit
50
shown in
FIG. 2
may be used for the boot circuit
18
of FIG.
1
. Prior to the DR signal going high, a boot-node
52
is precharged to a voltage (VCC−Vtc) by the diode connected charging transistor
54
, where Vtc is the threshold voltage of the charging transistor
54
. When the DR signal goes high, an inverter
56
turns ON a PMOS pass transistor
62
to couple the boot-node
52
to the gate of the NMOS pull-up transistor
20
(FIG.
1
), and also turns OFF an NMOS discharging transistor
64
. An inverter
58
drives one terminal of a capacitor
60
coupled to the boot-node
52
, and thus, forces the boot-node
52
to a voltage in excess of the precharge voltage. The resulting voltage is used to drive the gate of the pull-up transistor
20
.
When the DR signal goes low, the inverter
56
turns ON the discharging transistor
64
to couple the gate of the pull-up transistor
20
to ground. The inverter
56
also applies a voltage of VCC to the gate of the pass transistor
62
in an attempt to turn OFF the pass transistor
62
to isolate the boot-node
52
. The inverter
58
then subsequently pulls the terminal of the capacitor
60
, to which its output is coupled, to approximately ground and, in response, a corresponding decrease in the voltage of the boot-node
52
will occur. Consequently, the resulting voltage of the boot-node
52
may be pulled below the precharge voltage. However, just prior to the output of the inverter
58
switching to ground potential, the voltage at the boot-node
52
will be well above VCC+Vt, where Vt is the threshold voltage of the pass transistor
62
. Thus, the pass transistor
62
will be on until the output of the inverter
58
switches to ground even though the inverter
56
app
Dinh Son T.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
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