Circuit and method for a folded bit line memory using trench pla

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257296, 257301, H01L 27108

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059145110

ABSTRACT:
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. A body contact is coupled to the body region of the access transistor that provides a body bias to the access transistor. The access transistor further includes a gate coupled to a word line disposed adjacent to the body region. A passing word line is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. A trench capacitor is also included. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor and a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.

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