Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1997-10-06
2000-05-23
Tran, Minh Loan
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257303, 257309, H01L 27108, H01L 2976, H01L 2994, H01L 31119
Patent
active
060668695
ABSTRACT:
A memory cell for a memory array in a folded bit line configuration. The memory cell includes an access transistor formed in a pillar of single crystal semiconductor material. The access transistor has first and second source/drain regions and a body region that are vertically aligned. The access transistor further includes a gate coupled to a wordline disposed adjacent to the body region. The memory cell also includes a passing wordline that is separated from the gate by an insulator for coupling to other memory cells adjacent to the memory cell. The memory cell also includes a trench capacitor. The trench capacitor includes a first plate that is formed integral with the first source/drain region of the access transistor. The trench capacitor also includes a second plate that is disposed adjacent to the first plate and separated from the first plate by a gate oxide.
REFERENCES:
patent: 4051354 (1977-09-01), Choate
patent: 4604162 (1986-08-01), Sobczak
patent: 4663831 (1987-05-01), Birrittella et al.
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4761768 (1988-08-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4920065 (1990-04-01), Chin et al.
patent: 4958318 (1990-09-01), Harari
patent: 4987089 (1991-01-01), Roberts
patent: 5001526 (1991-03-01), Gotou
patent: 5006909 (1991-04-01), Kosa
patent: 5017504 (1991-05-01), Nishimuro et al.
patent: 5021355 (1991-06-01), Dhong et al.
patent: 5028977 (1991-07-01), Kenneth et al.
patent: 5057896 (1991-10-01), Gotou
patent: 5072269 (1991-12-01), Hieda
patent: 5102817 (1992-04-01), Chatterjee et al.
patent: 5110752 (1992-05-01), Lu
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5177028 (1993-01-01), Manning
patent: 5177576 (1993-01-01), Kimura et al.
patent: 5202278 (1993-04-01), Mathews et al.
patent: 5208657 (1993-05-01), Chatterjee et al.
patent: 5216266 (1993-06-01), Ozaki
patent: 5223081 (1993-06-01), Doan
patent: 5266514 (1993-11-01), Tuan et al.
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5320880 (1994-06-01), Sandhu et al.
patent: 5327380 (1994-07-01), Kersh, III et al.
patent: 5376575 (1994-12-01), Kim et al.
patent: 5391911 (1995-02-01), Beyer et al.
patent: 5392245 (1995-02-01), Manning
patent: 5393704 (1995-02-01), Huang et al.
patent: 5396093 (1995-03-01), Lu
patent: 5410169 (1995-04-01), Yamamoto et al.
patent: 5414287 (1995-05-01), Hong
patent: 5422499 (1995-06-01), Manning
patent: 5427972 (1995-06-01), Shimizu et al.
patent: 5432739 (1995-07-01), Pein
patent: 5438009 (1995-08-01), Yang et al.
patent: 5440158 (1995-08-01), Sung-Mu
patent: 5445986 (1995-08-01), Hirota
patent: 5460316 (1995-10-01), Hefele
patent: 5460988 (1995-10-01), Hong
patent: 5466625 (1995-11-01), Hsieh et al.
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5483487 (1996-01-01), Sung-Mu
patent: 5492853 (1996-02-01), Jeng et al.
patent: 5495441 (1996-02-01), Hong
patent: 5497017 (1996-03-01), Gonzales
patent: 5504357 (1996-04-01), Kim et al.
patent: 5508219 (1996-04-01), Bronner et al.
patent: 5508542 (1996-04-01), Geiss et al.
patent: 5519236 (1996-05-01), Ozaki
patent: 5528062 (1996-06-01), Hsieh et al.
patent: 5563083 (1996-10-01), Pein
patent: 5574299 (1996-11-01), Kim
patent: 5593912 (1997-01-01), Rajeevakumar
patent: 5616934 (1997-04-01), Dennison et al.
patent: 5640342 (1997-06-01), Gonzalez
patent: 5644540 (1997-07-01), Manning
patent: 5646900 (1997-07-01), Tsukude et al.
patent: 5691230 (1997-11-01), Forbes
patent: 5705415 (1998-01-01), Orlowski et al.
Hu, G., et al., "Evening Panel Discussion--Will Flash Memory Replace Hard Disk Drive", IEDM Technical Digest, (Dec. 11, 1994).
Sun, J., "CMOS Technology for 1.8C and Beyond", Int'l Symp on VLSI Technology, Systems and Applications: Digest of Technical Papers, 293-297, (1997).
Takao, Y., et al., "A 4--um Full-CMOS SRAm Cell Technology for 0.2-um high Performance Logic LSIs", 1997 Symp. on VLSI Technology: Digest of Technical Papers, Kyoto, JP, 11-12, (1997).
Asai, S., et al., "Technology Challenges for Integration Near and Below 0.1 micrometer", Proceedings of the IEEE, 85, Special Issue on Nanometer-Scale Science & Technology, 505-520, (Apr. 1997).
Blalock, T.N., et al., "A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier", IEEE Journal of Solid-State Circuits, 27, 618-625 (Apr. 1992).
Bomchil, G., et al., "Porous Silicon: The Material and its Applications in Silicon-On-Insulator Technologies", Applied Surface Science, 41/42, 604-613 (1989).
Burnett, D., et al., "Implications of Fundamental Threshold Voltage Variations for High-Density SRAM and Logic Circuits", 1994 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 15-16, (Jun. 4-7, 1994).
Burnett, D., et al., "Statistical Threshold-Voltage Variation and its Impact on Supply-Voltage Scaling", SPIE, 2636, 83-90, (1995).
Chen, M.J., et al., "Back-Gate Forward Bias Method for Low-Voltage CMOS Digital Circuits", IEEE Transactions on Electron Devices, 43, 904-909, (Jun. 1986).
Chen, M.J., et al., "Optimizing the Match in Weakly Inverted MOSFET'S by Gated Lateral Bipolar Action", IEEE Transactions on Electron Devices, 43, 766-773, (May 1996).
Chung, I.Y., et al., "A New SOI Inverter for Low Power Applications", Proceedings of the 1996 IEEE International SOI Conference, Sanibel Island, FL, 20-21, (Sep. 30--Oct. 3, 1996).
De, V.K., et al., "Random MOSFET Parameter Fluctuation Limits to Gigascale Integration (GSI)", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 198-199, (Jun. 11-13, 1996).
Denton, J.P., et al., "Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate", IEEE Electron Device Letters, 17, 509-511, (Nov. 1996).
Fong, Y., et al., "Oxides Grown on Textured Single-Crystal Silicon--Dependence on Process and Application in EEPROMs", IEEE Transactions on Electron Devices, 37, 583-590, (Mar. 1990).
Fuse, T., et al., "A 0.5V 200MHz 1-Stage 32b ALU Using a Body Biss Controlled SOI Pass-Gate Logic", 1997 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 286-287, (1997).
Gong, S., et al., "Techniques for Reducing Switching Noise in High Speed Digital Systems", Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit, 21-24, (1995).
Hao, M.V., et al., "Electrical Characteristics of Oxynitrides Grown on Textured Single-Crystal Silicon", Appl. Phys. Lett., 60, 445-447, (Jan. 1992).
Harada, M., et al., "Suppression of Threshold Voltage Variation in MTCMOS/SIMOX Circuit Operating Below 0.5 V", 1996 Symposium on VLSI Technology, Digest of Technical Papers, Honolulu, HI, 96-97 (Jun. 11-13, 1996).
Hisamoto, D., et al., "A New Stacked Cell Structure for Giga-Bit DRAMs using Vertical Ultra-Thin SOI (DELTA) MOSFETs", 1991 IEEE International Electron Devices Meeting, Technical Digest, Washington, D.C., 959-961, (Dec. 8-11, 1991).
Hodges, D.A., et al., "MOS Decoders", In: Analysis and Design of Digital Integrated Circuits, 2nd Edition, McGraw-Hill Book Co., New York, 354-357, (1988).
Holman, W.T., et al., "A Compact Low Noise Operational Amplifier for a 1.2 Micrometer Digital CMOS Technology", IEEE Journal of Solid-State Circuits, 30, 710-714, (Jun. 1995).
Hu, G., et al., "Will Flash Memory Replace Hard Disk Drive?", 1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline, 1 p., (Dec. 13, 1994).
Huang, W.L., et al., "TFSOI Complementary BiCMOS Technology for Low Power Applications", IEEE Transactions on Electron Devices, 42, 506-512, (Mar. 1995).
Jun, Y.K., et al., "The Fabrication and Electrical Properties of Modulated Stacked Capacitor for Advanced DRAM Applications", IEEE Electron Device Letters, 13, 430-432, (Aug. 1992).
Jung, T.S., et al., "A 117-mm.sup.2 3.3-V Only 128-Mb Multilevel NAND Flash Memory for Mass Storage Applications", IEEE Journal of Solid-State Circuits, 31, 1575-1582, (Nov. 1996).
Kang, H.K., et al., "Highly Manufacturable Process Technology for Reliable 256 Mbit and 1Gbit DRAMs", IEEE International Electron Devices Meeting, Technical Digest, San Francisco,
Forbes Leonard
Noble Wendell P.
Micro)n Technology, Inc.
Nguyen Cuong Quang
Tran Minh Loan
LandOfFree
Circuit and method for a folded bit line memory cell with vertic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit and method for a folded bit line memory cell with vertic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit and method for a folded bit line memory cell with vertic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1838757