Circuit and associated methodology

Details Circuit and associated methodology Circuit and associated methodology

2005-09-20

2005-09-20

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

C326S121000

Reexamination Certificate

active

06946877

ABSTRACT:
A method of interstitial pre-discharge in a circuit includes providing the circuit, which includes a pre-charge node coupled to a clock evaluate node operable to receive a clock evaluate input cycle. Multiple pull-down stacks each including an interstitial node interconnect between the pre-charge node and ground. The interstitial node of each pull-down stack couples to an interstitial discharger device gated to ground. The method further includes operating the circuit in a pre-charge phase of the clock evaluate input cycle, including pre-charging the pre-charge node and the interstitial nodes, and keeping the devices in the pull-down stacks and the interstitial dischargers in a high impedance state. The method additionally includes operating the circuit in an evaluate phase of the clock cycle, including discharging the pre-charge node to ground through a pull-down stack, and discharging the interstitial node to ground through the interstitial discharger device to preclude charge share.

REFERENCES:
patent: 6002271 (1999-12-01), Chu et al.
patent: 6201425 (2001-03-01), Kartschoke et al.
patent: 6441646 (2002-08-01), Braceras et al.

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