Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
1997-04-22
2001-08-28
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S690000, C257S723000, C361S749000
Reexamination Certificate
active
06281577
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a process for the formation of a spatial chip arrangement and to a spatially constructed chip arrangement.
With the increasing miniaturisation of electronic appliances such as portable telephones for example, also generally designated as “handy”, or portable computers, known by the expression “notebook”, the demands as regards the integration density of the electronic modules employed therein also increase. To a particular degree this is unquestionably the case with memory modules which are utilised in such appliances or memory expansions which may be used optionally. At the present time, by way of structural design for such highly integrated memory modules use is made as a rule of so-called “multi-chip modules” (MCM) in which the individual chips are arranged above one another and electrically connected to one another. By reason of the high integration density—that is to say, the arrangement of a plurality of chips within an extremely small space—the probability of failure of such a memory module also increases of course, since for failure of a component it is sufficient if only one of the chips which are processed in a plurality is defective. In order to be able to eliminate failure of a component to the greatest possible extent during operation of the highly integrated modules, an examination of the modules has hitherto been undertaken after completion and prior to delivery or incorporation into the electronic appliance in question. This is associated, on the one hand, with an additional component test following the actual manufacturing process. On the other hand, the implementation of a component test only after finishing the complete component means that in the event of a component failure, which as a rule is caused only by the failure of an individual chip, the entire component is rejected.
SUMMARY OF THE INVENTION
The object underlying the present invention is therefore to propose a process for the formation of a spatial chip arrangement and also a spatial chip arrangement which, in either case, despite the fact that a high integration density is achieved, creates an opportunity for the early detection of faults so that classification of the complete component as a reject can be prevented to the greatest possible extent.
This object is achieved, respectively, by means of a process having the characteristics of claim
1
and by means a chip arrangement having the characteristics of claim
11
.
In accordance with the invention it is proposed, with a view to forming a spatial chip arrangement having several chips arranged in various planes and electrically connected to one another, to contact the chips via the peripheral connection surfaces with assigned conducting paths of a conducting-path structure that is arranged on at least one carrier substrate. In this regard the chips may be arranged either transverse to the rectilinearly aligned carrier substrate or parallel to the longitudinal extent of a flexible carrier substrate.
Both alternatives according to the invention offer, on the one hand, the possibility of arranging the chips in a space-saving structure and, on the other hand, the possibility of a simple electrical examination, during manufacture of the stacked chip arrangement, of the chip that is connected to the carrier substrate.
The space-saving arrangement of the chips is created, in the one case, by the transverse arrangement of the chips relative to the longitudinal extent of the carrier substrate and, in the other case, by the fact that after establishment of the connection of the chips to the flexible carrier substrate the carrier substrate can, by reason of its flexibility, be arranged so as to correspond to the desired spatial arrangement of the chips with arbitrary changes of direction of the longitudinal extent. For instance, the flexible carrier substrate can be arranged in meandering form or even in helical form, which results in a high spatial integration density for the chips.
In the one case a particularly high integration density can be produced by the chips being brought with their peripheral connection surfaces arranged along a lateral edge into a connecting position adjacent to the conducting paths and transverse to the longitudinal extent of the conducting paths and then by a connection being effected between pairings, assigned respectively to one another, of conducting path and connection surface via a connecting material that is applied between the respective conducting path and the assigned connection surface.
In the other case a particularly high integration density can be achieved by the chips being contacted parallel to the longitudinal extent of the carrier substrate with their connection surfaces on conducting paths of conducting-path structures arranged on both sides of the carrier substrate and, after the chips have been brought into contact, by a meandering arrangement of the carrier substrate being effected with a view to forming the spatial chip arrangement.
The implementation of the two aforementioned process alternatives proves to be particularly advantageous if, after a chip has been brought into contact with the carrier substrate, an electrical examination of the chip is carried out via the connecting-path structure of the carrier substrate that is connected to a test device.
Irrespective of the relative arrangement of the chips in relation to the carrier substrate it proves to be advantageous if, with a view to preparing the contacting of the chips, the carrier substrate or substrates is/are fixed with one end in a clamping device. Hence the clamping device may also be used as a test device.
In particular in the case where it is a question of chips with reverse-side metallisation it proves to be advantageous if in each case prior to making contact with an additional chip a spacer device is arranged on the upper side of the previously contacted chip. On the one hand, given a suitable choice of material for the spacer device, an insulation between the chips is achieved. On the other hand, a static stabilisation of the stacked structure of the chip arrangement is also made possible. This stabilisation effect can be intensified still further if an adhesive material, for example an application of adhesive, is chosen for the spacer device.
In the case where a soldering material is used by way of connecting material it proves to be advantageous if the connecting material is applied in the form of isolated deposits of connecting material onto the conducting paths and/or the connection surfaces and is then activated by remelting. This type of application of deposits of soldering material is particularly suitable in the case where the chips are arranged transverse to the longitudinal extent of the carrier substrate. In the case where the chips are arranged parallel to the longitudinal extent of the flexible carrier substrate, with a view to connecting the chips to the carrier substrate a so-called “face-down technology” for establishing the connection, such as the “flip-chip process” for example, proves particularly suitable. Another possibility consists in the use of an adhesive material which is cured by UV irradiation—that is to say, is activated with a view to establishing a durable connection.
In order, finally, to enable an external contacting of the spatial chip arrangement that is as simple as possible, it proves to be particularly advantageous if, after the last chip has been brought into contact, a projecting length of the carrier substrate is firstly folded over the upper side of the chip and connected to the upper side and then a through-contact is made from the reverse side of the carrier substrate onto the conducting-path structure of the carrier substrate that is connected to the chip-connection surfaces. Alternatively it is also possible to make use, right from the beginning, of carrier substrates that are provided with an appropriate through-contact.
An advantageous alternative to this is obtained if, with a view to forming an external-contact arrangement o
Azdasht Ghassem
Kasulke Paul
Oppermann Hans-Hermann
Zakel Elke
Chambliss Alonzo
Chaudhuri Olik
Darby & Darby
Pac Tech-Packaging Technologies GmbH
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