Chip testing within a multi-chip semiconductor package

Details Chip testing within a multi-chip semiconductor package Chip testing within a multi-chip semiconductor package

2006-11-21

2006-11-21

Lamarre, Guy (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S025000, C365S201000

Reexamination Certificate

active

07139945

ABSTRACT:
A system and method is provided for testing a secondary chip housed within a multi-chip packaged semiconductor device. The packaged semiconductor device includes a secondary chip and a primary chip, with the secondary chip communicating with the primary chip through signal drivers. The secondary chip also includes at least one test signal driver connected to the signal drivers and to certain external connectors that may be shared with the primary chip. The test signal drivers provide testing of the secondary chip using standard integrated circuit test equipment while the secondary chip is contained within the packaged semiconductor device.

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