Chip structure and process for forming the same

Details Chip structure and process for forming the same Chip structure and process for forming the same

2003-01-06

2004-09-28

Zarneke, David A. (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

Reexamination Certificate

active

06798073

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a chip structure and a process for forming the same. More particularly, the invention relates to a chip structure for improving the resistance-capacitance delay and a forming process thereof.
2. Description of the Related Art
Nowadays, electronic equipment are increasingly used to achieve many various tasks. With the development of electronics technology, miniaturization, multifunction task, and comfort of utilization are among the principle guidelines of electronic product manufacturers. More particularly in semiconductor manufacture process, the semiconductor units with 0.18 microns have been mass-produced. However, the relatively fine interconnections therein negatively impact the chip. For example, this causes the voltage drop of the buses, the resistance-capacitor delay of the key traces, and noises, etc.
FIG. 1
is a cross-sectional view showing a conventional chip structure with interconnections.
As shown in
FIG. 1
, a chip structure
100
is provided with a substrate
110
, an built-up layer
120
and a passivation layer
130
. There are plenty of electric devices
114
, such as transistors, on a surface
112
of the substrate
110
, wherein the substrate
110
is made of, for example, silicon. The built-up layer
120
provided with a dielectric body
122
and an interconnection scheme
124
is formed on the surface
112
of the substrate
110
. The interconnection scheme
124
interlaces inside the dielectric body
122
and is electrically connected to the electric devices
114
. Further, the interconnection scheme
124
includes many conductive pads
126
exposed outside the dielectric body
122
and the interconnection scheme
124
can electrically connect with external circuits through the conductive pads
126
. The dielectric body
122
is made of, for instance, silicon nitride or silicon oxide. In addition, the passivation layer
130
is deposited on the built-up layer
120
, and has many openings respectively exposing the conductive pads
126
. The interconnection scheme
124
includes at least one metal layer that can serve as a power bus or a ground bus. The power bus or the ground bus is connected to at least one of the conductive pads
126
through which the power bus or the ground bus can electrically connect with external circuits.
However, as far as the chip structure
100
is concerned, resistance-capacitance (RC) delay is easily generated because the line width of the interconnection scheme
124
is extremely fine, about below 0.3 microns, the thickness of the interconnection scheme
124
is extremely thin, and the dielectric constant of the dielectric body
122
is extremely high, about 4. Therefore, the chip efficiency drops off. In particular, the RC delay even usually occurs with respect to a power bus, a ground bus or other metal lines transmitting common signals. In addition, the production of the interconnection scheme
124
with extremely fine line width is necessarily performed using facilities with high accuracy. This causes production costs to dramatically rise.
The present invention is related to a R.O.C. patent application Ser. No. 88120548, filed Nov. 25, 1999, by M. S. Lin, issued Sep. 1, 2001, now R.O.C. Pat. No.140721. R.O.C. patent application Ser. No. 88120548 claims the priority of pending U.S. patent application Ser. No. 09/251,183 and the subject matter thereof is disclosed in pending U.S. patent application Ser. No. 09/251,183. The present invention is related to a R.O.C. patent application Ser. No.90100176, filed Jan. 4, 2001, by M. S. Lin and J. Y. Lee, now pending. The subject matter of R.O.C. patent application Ser. No.90100176 is disclosed in pending U.S. patent application Ser. No. 09/691,497. The present invention is related to a Japanese patent application Ser. No.200156759, filed Mar. 1, 2001, by M. S. Lin and J. Y. Lee, now pending. The present invention is related to a European patent application Ser. No.01480077.5, filed Aug. 27, 2001, by M. S. Lin and J. Y. Lee, now pending. The present invention is related to a Singaporean patent application Ser. No.200101847-2, filed Mar. 23, 2001, by M. S. Lin and J. Y. Lee, now pending. Japanese patent application Ser. No.200156759, European patent application Ser. No.01480077.5, and Singaporean patent application Ser. No. 200101847-2 claim the priority of pending U.S. patent application Ser. No. 09/691,497 and the subject matter of them is disclosed in pending U.S. patent application Ser. No. 09/691,497.
SUMMARY OF THE INVENTION
Accordingly, an objective of the present invention is to provide a chip structure and a process for forming the same that improves resistance-capacitance delay and reduces energy loss of the chip.
Another objective of the present invention is to provide a chip structure and a process for forming the same that can be produced using facilities with low accuracy. Therefore, production costs can substantially reduce.
To achieve the foregoing and other objectives, the present invention provides a chip structure that comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers. In addition, the first dielectric body is constructed from at least one first dielectric layer, and the second dielectric body is constructed from at least one second dielectric layer. The individual second dielectric layer is thicker than the individual first dielectric layer.
According to a preferred embodiment of the present invention, the thickness of the traces of the second metal layer ranges from 1 micron to 50 microns; the width of the traces of the second metal layer ranges from 1 micron to 1 centimeter; the cross sectional area of the traces of the second metal layer ranges from 1 square micron to 0.5 square millimeters. The first dielectric body is made of, for example, an inorganic compound, such as a silicon nitride compound or a silicon oxide compound. The second dielectric body is made of, for example, an organic compound, such as polyimide (PI), benzocyclobutene (BCB), porous dielectric material, or elastomer. In addition, the above chip structure further includes at least one electrostatic discharge (ESD) circuit and at least one transitional unit that are electrically connected to the first interconnection scheme. The transitional unit can be a driver, a receiver or an I/O circuit. Moreover, the first interconnection scheme include at least one first conductive pad, at least one second conductive pad, and at least one linking trace, wherein the openings of the passivation layer expose the first conductive pad and the second conductive pad. The second conductive pad is electrically connected to the second interconn

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