Chip stack package

Details Chip stack package Chip stack package

2008-07-10

2011-10-18

Lee, Eugene (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With electrical contact in hole in semiconductor

C257S686000, C257S777000, C257SE23169, C257SE25006, C257SE25013, C257SE25021

Reexamination Certificate

active

08039928

ABSTRACT:
A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

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patent: 2004/0251529 (2004-12-01), Lee et al.
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patent: 2004-134679 (2004-04-01), None
patent: 2004-152810 (2004-05-01), None
patent: 2006-173388 (2006-06-01), None
English language abstract of Japanese Publication No. 2004-134679.
English language abstract of Japanese Publication No. 2004-152810.
English language abstract of Japanese Publication No. 2006-173388.

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