Chip scale package with compliant leads

Details Chip scale package with compliant leads Chip scale package with compliant leads

2005-05-31

2005-05-31

Brock, II, Paul E (Department: 2815)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having air-gap dielectric

C438S461000, C438S611000, C438S619000

Reexamination Certificate

active

06900110

ABSTRACT:
A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.

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