Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-08-31
2001-09-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S106000, C438S109000, C438S110000
Reexamination Certificate
active
06284566
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor packages and methods of fabrication thereof, and more particularly to a low cost packages adaptable to low input/output count devices.
BACKGROUND OF THE INVENTION
Plastic ball grid array devices (PBGA) provide has a large number of advantages over other package types, e.g. pin grid arrays. In a typical PBGA package
10
(FIG.
2
), a printed circuit board (PCB) made from such material as bismaleimide triazine (BT) resin or ceramic (Al
2
O
3
) is used as a substrate
12
. In such a package, a silicon integrated circuit (IC) die is attached on one side of substrate
12
, with solder balls on the opposite side of substrate
12
, and the silicon IC is encapsulated by a molding compound
14
.
Electrical connection between the silicon IC die and the solder balls are achieved by wire bonding, or by means of a flip-chip connection, to conductors or traces on the “die side” surface of substrate
12
, from such conductors to traces, and then through vias to the opposite side of substrate
12
, at which other conductors or traces are provided to couple the solder balls.
At present, BGA technology is cost-effective for applications in which a large number of “I/Os” or “pins” per package are required. For example, popular BGA packages include 119, 169, 225, 256, 313, 352, 420 or 625 balls. Although semiconductor devices requiring a lower number of I/O pins are very common, it is expensive to provide BGA packages at such low number of I/O's. If BT is used as the material for substrate
12
, for example, the BT material cost may account for 50% of the package.
Typically, BT or ceramic is provided in single-element form
16
(
FIG. 1
) with dimensions of, for example, 45 mm by 187.5 mm. A manufacturer of BGA packages attempts to lay out the packages to maximize area utilization of element
16
. In element
16
, the completed devices
10
are singulated (indicated by the dotted lines
17
on the element
16
) to result in individual BGA devices
10
(FIG.
2
). The remaining portions of element
16
are simply discarded. Such discarded portions may amount to 20 to 40% of the total area of element
16
. Clearly, therefore, minimize such discarded portions of the element
16
would significantly reduce manufacturing cost, making the significant advantages of PBGA packages available to smaller packages.
SUMMARY OF THE INVENTION
The present invention provides an assembly process for manufacturing chip scale packages. The assembly process includes the steps of: (i) providing a perforated substrate; (ii) attaching to the perforated substrate a plurality of semiconductor dies; (iii) providing an electrically insulative covering over the plurality of semiconductor dies to form a sealed structure which includes the insulative covering and the perforated substrate, so as to enclose the semiconductor dies; and (iv) singulating the sealed structure into chip scale packages, such that each chip scatle package includes one of the semiconductor dies. In one embodiment, the perforated substrate is provided a conductive pattern for connecting the terminals of the semiconductor dies. In one implementation, the conductive pattern is a metallic bondable structure, to allow wire bonding to the bonding pads of the integrated circuit on the semiconductor die.
According to another aspect of the present invention, preformed bumps or vias can be provided in the perforated substrate, to enhance efficiency in the assembly process.
The assembly process of the present invention allows an electrical testing step to be performed prior to performing singulation. In this manner, efficiency and cost savings can be achieved by testing a large number of integrated circuit dies in parallel, and without incurring the costs of customized receptacles for holding the individual integrated circuits during testing.
The singulation step of the assembly process-of the present invention can be achieved by an inexpensive sawing step using a diamond saw with serrated blades. The chip scale packages can be (i) encapsulated in plastic, using a transfer molding method, (ii) protected by a die coating using, for example, a screening process, or (iii) hermetically sealed using a ceramic cap and a suitable sealant.
In accordance with another aspect of the present invention, the present invention provides a chip scale package which includes (i) a perforated substrate; (ii) an electrically conductive pattern on one side of the perforated substrate, for providing a first set of electrically conductive paths from selected positions of the conductive pattern to the through holes in the perforated substrate; (iii) a solder mask to provide access from the bonding pads of the integrated circuit die to the selected positions; (iv) external terminals coupled to the conductive pattern to provide a second set of conductive paths in the through holes of the perforated substrate; and (v) a covering provided to form, in conjunction with the substrate, an enclosure enclosing the integrated circuit die and the first and second sets of electrically conductive paths, exposing only the external terminals. In such a chip scale package, the external terminals can be provided by solder balls, and the second set of conductive paths can be provided by through hole plating or a solder flux.
The present invention can be used to provide a package in which the integrated circuit die is attached to the solder mask in either a “die-up” configuration or a “die-down” configuration. The electrical connections between the bonding pads of the integrated circuit die and the first set of conductive patterns can be provided by bond wires between the bonding pads and the conductive patterns on the perforated substrate, accessed through openings in the solder mask.
The present invention provides (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a footprint minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process, resulting in a very high throughput.
The present invention provides chip scale packages that are assembled in a particularly efficient manufacturing process and minimizes wastage of packaging material.
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Lee Shaw Wei
Mathew Ranjan J.
Takiar Hem P.
Kwok Edward C.
National Semiconductor Corporation
Skjerven Morrill & MacPherson LLP
Smith Matthew
Yevsikov Victor V.
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