Chip-packaging substrate and test method therefor

Details Chip-packaging substrate and test method therefor Chip-packaging substrate and test method therefor

2003-03-12

2004-03-16

Gibson, Randy (Department: 2841)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C361S760000, C361S761000, C361S762000, C361S764000, C361S783000, C361S750000, C361S751000, C174S255000, C174S260000, C174S261000

Reexamination Certificate

active

06707677

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip-packaging substrate, and in particular to a chip-packaging substrate having a test circuit for failure controls.
2. Description of the Related Art
As electronic devices become thinner and smaller, printed circuit boards (PCB) are required to be thinner, with narrower wires and intervals. At the present, one of the most popular chip packages is the plastic ball grid array (PBGA) package. PBGA packages address the need for increased pin counts, such that package size is nearly identical to those packaged by previous methods.
FIG. 1A
is schematic top view of a conventional PBGA substrate.
FIG. 1B
shows a chip-packaging unit from FIG.
1
A. The PBGA substrate shown in
FIG. 1A
is the substrate used in package factories, provided by PCB suppliers. The PBGA substrate includes, but is not limited to, four chip-packaging units
10
for four IC chips. The chip-packaging unit
10
includes a square package area
12
with an enclosed connection area
11
. The package area
12
has a plurality of pads
121
arranged in array. The connection area
11
connects the package areas
12
for packaging facilities to secure the PBGA substrate when packaging chips, after which the connection area
11
is discarded, becoming waste material.
However, PBGA substrates are multilayer structures (more than 8 layers) with thickness about 0.5 mm and wire width and intervals less than 0.1 mm. PBGA substrates must withstand high temperatures, high humidity, and strong acidity and alkalinity during PCB fabrication. PBGA substrates are easily deformed and delaminated by high temperatures, causing defects when stacking wire and insulation layers.
Previously, PBGA substrates could only be tested after chips were completely packaged on the package areas. The result of the test only shows whether the packaged chips work or not, without individually identifying whether defects are caused by chips, PBGA substrates or the packaging process. Therefore, the yield ratio of the PBGA packaged chips is higher than the sum of the yield ratio of each individual part. The cost of PBGA packages is thus higher than other conventional package methods.
Referring to
FIG. 1A
, the package areas
12
and the connection area
11
of the PBGA substrate are formed by the same fabrication method at the same time. The connection area
11
also has the same wire layers and insulation layers in the package areas
12
. The difference between the package areas
12
and the connection area
11
is that the connection area
11
does not have a predetermined circuit and will be discarded as waste material after chips are packaged on the package areas.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide chip-packaging substrates having a test circuit on the connection area, which will be discarded after the chip package process, to pre-test the PBGA substrates, and filter out damaged substrates, thereby reducing the cost of the PBAG packaged chips.
The present invention provides a chip-packaging substrate having a package area, connection area and test circuit. The connection area is connected to and enclosed by the package areas. A test circuit is arranged within the connection area, passing through at least two wire layers and the insulation layer therebetween. The test circuit electrically connects the first electrodes. Failure of the chip-packaging substrate is detected when the test circuit is open between any two electrodes.
According to another embodiment of the invention, the chip-packaging substrate comprises a plurality of package areas connected by a connection area. As well, the connection area has a plurality of electrodes and a test circuit passing through at least two wire layers and the insulation layer therebetween and electrically connecting the electrodes.
The present invention also provides a method for testing chip-packaging substrates. The method first comprises providing a chip-packaging substrate with a connection area enclosing a plurality of package areas. The connection area has a plurality of electrodes connected by a test circuit. Next, the conductivity between two selected electrodes is checked. Finally, failure of the chip-packaging substrate is detected when the test circuit is open between the two selected electrodes.
According to the embodiments of the invention, the second insulation surface has a plurality of second electrodes. The test circuit electrically connects the second electrodes. The package area has a plurality of insulation layers and wire layers extending from the connection area. The insulation layers comprise macromolecular compounds.
Furthermore, the connection area has a plurality of through holes, such that the test circuit electrically connects the wire layers thereby. The connection area also has a plurality of blind via holes, such that the test circuit can electrically connect any two wire layers thereby. The package area has a predetermined circuit, and the predetermined circuit and the test circuit are formed at the same time.
A detailed description is given in the following embodiments with reference to the accompanying drawings.


REFERENCES:
patent: 5307012 (1994-04-01), Bhattacharyya et al.
patent: 5378981 (1995-01-01), Higgins, III
patent: 6351392 (2002-02-01), Palaniappa
patent: 6427222 (2002-07-01), Shau
patent: 6566899 (2003-05-01), Tamaru et al.

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