Chip package without core and stacked chip package structure...

Details Chip package without core and stacked chip package structure... Chip package without core and stacked chip package structure...

2005-12-13

2008-10-14

Parekh, Nitin (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Die bond

C257S787000, C257S784000, C257S780000, C257SE23024

Reexamination Certificate

active

07436074

ABSTRACT:
A chip package without a core, including a patterned circuit layer, a chip, a solder mask, a molding compound and multiple outer terminals, is provided. The patterned circuit layer has a first surface and a second surface opposite to each other. The chip disposed on the first surface is electrically connected to the patterned circuit layer. The solder mask disposed on the second surface has a plurality of first openings by which part of the patterned circuit layer is exposed. The molding compound with a plurality of through holes cover the pattern circuit layer and fix the chip onto the patterned circuit layer. Each outer terminal disposed in the through hole is electrically connected to the patterned circuit layer.

REFERENCES:
patent: 5668405 (1997-09-01), Yamashita
patent: 5956233 (1999-09-01), Yew et al.
patent: 6048755 (2000-04-01), Jiang et al.
patent: 6448506 (2002-09-01), Glenn et al.
patent: 7078794 (2006-07-01), Lee
patent: 7138724 (2006-11-01), Grigg et al.
patent: 7291925 (2007-11-01), Han et al.
patent: 2005/0253284 (2005-11-01), Wang et al.

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