Chip package and package process thereof

Details Chip package and package process thereof Chip package and package process thereof

2006-08-14

2008-10-07

Nguyen, Ha (Department: 2829)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C257S777000

Reexamination Certificate

active

07432127

ABSTRACT:
A chip package and a package process thereof are provided. The chip package comprises a package substrate, a chip, a plurality of spacers, an adhesive layer, and a plurality of wires. The package substrate has a carrying surface. The chip is disposed on the carrying surface. The spacers are formed between the chip and the carrying surface to maintain an interval between the chip and the package substrate. The adhesive layer is disposed between the chip and carrying surface to encapsulate the spacers. The chip is electrically connected to the package substrate via the wires.

REFERENCES:
patent: 6353263 (2002-03-01), Dotta et al.
patent: 6716667 (2004-04-01), Yamaguchi
patent: 10144722 (1998-05-01), None

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