Chip interconnect wiring structure with low dielectric...

Details Chip interconnect wiring structure with low dielectric... Chip interconnect wiring structure with low dielectric...

2000-11-17

2003-06-10

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S751000

Reexamination Certificate

active

06577011

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
This invention pertains to the field of microelectronic chip fabrication for logic, memory, communication and microcontroller applications.
2. Description of the Prior Art
The operating speeds of silicon integrated circuits are increasing at phenomenal rates to meet aggressive performance demands in computing, communication and microcontroller applications. This in turn necessitates that the signal propagation delays in the wiring that is used to interconnect the circuits on a chip be reduced so that the performance is not limited or hampered unduly by interconnect delays. Interconnect delays in chips are due to the RC time constants wherein R is the resistance of the on chip wiring and C is the effective capacitance between the signal lines and the surrounding conductors in the multilayer interconnection stack. The resistance of the wiring can be reduced by using a material with a lower specific resistivity than the currently used Al-rich Al—Cu alloys. Copper, which has half the specific resistivity of Al—Cu alloys, is the prime candidate being explored for this purpose. The capacitance of a signal line is a combination of the mutual capacitance between the lines in the same wiring plane (C
LL
) and between lines in two different levels (C
CO
or C
LG
) as shown in
FIG. 1
, cited from a recent conference (R. Havemann presented at the Proceedings of the 1996 Symposium on VLSI Technology, Honolulu, Hi., Jun. 10, 1996). As shown in the graph associated with this schematic, when feature sizes decrease, the intralevel capacitance C
LL
becomes the major part of the interconnect capacitance and hence dominates the interconnect delay. Interconnect capacitance can be reduced by reducing the dielectric constant, K, of the insulating medium that surrounds these lines. Hence, there has been a significant effort to identify and use low K insulators in interconnect structures. A whole gamut of insulator materials including fluorinated silica, polymers with and without fluorination, amorphous teflon-like polymers, and aerogels made of porous silica have been proposed as possible low K materials for this purpose.
Progress is being made in fabricating interconnect wiring with copper as the conductor. Since copper, unlike Al, is difficult to pattern by subtractive plasma etching, a “Damascene” process is favored to fabricate copper features embedded in a dielectric medium. One typical version of this process, known as the “dual damascene” process, is described briefly below as an example. After the devices are fully fabricated on a semiconductor wafer, the surface is coated with an ionic barrier such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or silicon nitride and appropriate vias are defined in this barrier by photolithography and etching at locations where contacts for interconnect wiring are required. Subsequently, the etched features are filled with an appropriate conductor such as tungsten.
For the sake of clarity and simplicity, we depict the wafer at this stage of processing as the semiconductor substrate,
10
, in
FIGS. 2A
to
2
D and later in
FIGS. 4A
to
4
D. Two layers of dielectrics,
20
and
30
, are applied on the semiconductor substrate and patterned by lithography and plasma etching to produce trenches,
50
, on the top layer that represent the wiring tracks and vias,
40
, in the lower layer that will become the means to connect the wires to the metal level below, as shown in FIG.
2
A. Layers
20
and
30
can be made of the same dielectric in which case they can be applied in a single deposition step. In a next step, an electrically conductive barrier/adhesion layer,
60
, and a copper-based conductor layer,
70
, are deposited on the patterned dielectric structure by one or more of the techniques such as sputtering and/or chemical vapor deposition and electrolytic or electroless plating. This layer has to be thick enough to overfill the vias,
40
, and trenches,
50
, as shown in FIG.
2
B.
The last step is to planarize the top surface by chemical-mechanical polishing (CMP) so that the excess copper and the barrier layer are polished off from the top surface resulting in the inlaid wire/via stack as shown in FIG.
2
C. This sequence is repeated several times till the necessary number of wiring layers are built. In a final step, the wafer is coated with an insulating passivation layer,
80
, and terminal metal pads,
90
, are deposited and connected to the top most wiring level through suitable vias in the passivation layer,
80
, as shown in FIG.
2
D. These terminal pads are used to assemble the chip on a chip carrier using solder interconnects which enables the chip to communicate with other chips and to send and receive information to the user. Alternate terminal pad processes and structures can also be used in place of the final step described above which enable interconnection using wire bonding, conductive paste bonding and the like. Usually, the wafers are subjected to a 400° C. anneal in a N
2
/H
2
mixture to “anneal out” any damage accumulated in the thin gate oxide under the silicon circuit gates due to the various plasma processes used to fabricate the wiring structure.
There are several practical difficulties in integrating the low K dielectric materials in such a wiring structure. First, the physico-chemical properties of many of these low K materials are not optimum for the CMP process. For example, most of the polymer materials are too soft and get eroded at too fast a rate relative to copper during CMP, to allow good control over the inlaid layer thickness. Fluorinated oxide dielectrics are suspected to react with or be prone to reaction with wiring metallurgies leading to corrosion and adhesion loss. Some of these issues can be contained by applying a hard mask layer over the dielectric to act as a CMP stop layer but this requires additional processing and one has to ensure compatibility of the low K material with the processing of this additional layer. Second, most of the low K polymers degrade under thermal excursions to temperature at or above 400° C. Hence, they are not suitable for the device interconnection application because they cannot withstand the device damage anneal alluded to above. This severely restricts the choice of dielectric, which can be used for this purpose. Last, the porous inorganic dielectrics such as aerogels are mechanically weak and friable and are unlikely to withstand the multilayer build process of repeated metal deposition and CMP described above.
Another concern is the penetration of copper into the dielectric materials during the various thermal excursions encountered or the fabrication of the interconnect stack and the final damage anneal step. This can degrade the insulator's dielectric constant and leakage performance and, in some cases, facilitate the migration of copper to the device levels during the service life of the chips, leading to device failure. Accordingly, the adhesion/barrier layer described above has to function as a copper diffusion barrier. To achieve this reliably, the adhesion/barrier layer has to be free of defects and rapid diffusion paths such as grain boundaries. This in turn requires conductive barrier films of sizable film thickness. Since the typical conductive barrier films have high electrical resistivity, the presence of a significant thickness of such a film in the conductor cross section leads to an increase in the effective line resistance of the wiring. This is particularly severe for narrow lines typical of advanced chips, where the barrier thickness becomes a significant fraction of the line width itself.
Many of the low K dielectrics are also not compatible with Al—Cu interconnect processing because 400° C. to 450° C. substrate temperatures during deposition and/or post deposition anneals are still required to achieve reliable microstructure and properties of the Al—Cu lines, and repeated excursions to such temperatures (in addition to the final device damage anneal) tend to lead to degradation of

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