Chip debugging using incremental recompilation

Details Chip debugging using incremental recompilation Chip debugging using incremental recompilation

2006-07-11

2006-07-11

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07076751

ABSTRACT:
While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.

REFERENCES:
patent: 4527234 (1985-07-01), Bellay
patent: 4696004 (1987-09-01), Nakajima
patent: 4788492 (1988-11-01), Schubert
patent: 4835736 (1989-05-01), Easterday
patent: 4847612 (1989-07-01), Kaplinsky
patent: 4873459 (1989-10-01), El Gamo et al.
patent: 5036473 (1991-07-01), Butts et al.
patent: 5058114 (1991-10-01), Kuboki et al.
patent: 5124588 (1992-06-01), Baltus et al.
patent: 5157781 (1992-10-01), Harwood et al.
patent: 5329470 (1994-07-01), Sample et al.
patent: 5365165 (1994-11-01), El-Ayat et al.
patent: 5425036 (1995-06-01), Liu et al.
patent: 5452231 (1995-09-01), Butts et al.
patent: 5568437 (1996-10-01), Jamal
patent: 5572712 (1996-11-01), Jamal
patent: 5629617 (1997-05-01), Uhling et al.
patent: 5640542 (1997-06-01), Whitsel et al.
patent: 5661662 (1997-08-01), Butts et al.
patent: 5717695 (1998-02-01), Manela et al.
patent: 5717699 (1998-02-01), Haag et al.
patent: 5764079 (1998-06-01), Patel et al.
patent: 5821771 (1998-10-01), Patel et al.
patent: 5870410 (1999-02-01), Norman et al.
patent: 5937190 (1999-08-01), Gregory et al.
patent: 5960191 (1999-09-01), Sample et al.
patent: 5983277 (1999-11-01), Heile et al.
patent: 6002861 (1999-12-01), Butts et al.
patent: 6014334 (2000-01-01), Patel et al.
patent: 6016563 (2000-01-01), Fleisher
patent: 6020758 (2000-02-01), Patel et al.
patent: 6104211 (2000-08-01), Alfke
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6157210 (2000-12-01), Zaveri et al.
patent: 6167561 (2000-12-01), Chen et al.
patent: 6182247 (2001-01-01), Herrmann et al.
patent: 6195788 (2001-02-01), Leaver et al.
patent: 6212650 (2001-04-01), Guccione
patent: 6223148 (2001-04-01), Stewart et al.
patent: 6247147 (2001-06-01), Beenstra et al.
patent: 6263484 (2001-07-01), Yang
patent: 6286114 (2001-09-01), Veenstra et al.
patent: 6317860 (2001-11-01), Heile
patent: 6321369 (2001-11-01), Heile et al.
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6460148 (2002-10-01), Veenstra et al.
patent: 6481000 (2002-11-01), Zaveri et al.
patent: 6490717 (2002-12-01), Pedersen et al.
patent: 6704889 (2004-03-01), Herrmann et al.
patent: 6754862 (2004-06-01), Hoyer et al.
patent: 6794896 (2004-09-01), Brebner
patent: 6891397 (2005-05-01), Brebner
patent: 6911841 (2005-06-01), Lee et al.
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 4042262 (1992-07-01), None
patent: 0 762 279 (1997-03-01), None
Marantz, Joshua, “Enhanced Visibility and Performance in Functional Verification by Reconstruction”, Proceedings of the 35thAnnual Conference on Design Automation Conference, pp. 164-169, Jun. 1998.
Stroud, Charles et al., “Evaluation of FPGA Resources for Built-in Self-test of Programmable Logic Blocks”, Proceedings of the 1996 ACM 4thInternational Symposium on Field-programmable Gate Arrays, 1996, pp. 1-7.
Collins, Robert R., “Overview of Pentium Probe Mode”, (www.x86.org/ariticles/problemd/ProbeMode.htm), Aug. 21, 1998, 3 pgs.
Collins, Robert R., “ICE Mode and the Pentium Processor”, (www.x86.org/ddj/Nov97/Nov97.htm), Aug. 21, 1986, 6 Pgs.
“PentiumPro Family Developer's Manual”, vol. 1: Specifications, Intel® Corporation, 1996, 9 Pgs.
Xilinx, Inc.; ISE Logic Design Tools: ChipScope, pp. 1-18, Nov. 2002.
Synplicity, Inc. “Identify™ RTL Debugger”, 2003; pp. 1-2, (www.symplicity.com/products/identify/index.html), Apr. 3, 2003.
Altera, Signal Tap Analysis in the Quartus II Software Version 2.0; Sep. 2002; Version. 2.1; Altera Corporation, pp. 1-14.
Praveen K. Jaini and Nur A. Touba; “Observing Test Response of Embedded Cores through Surround Logic”; 1999 IEEE, pp. I-119-I-123.
Nur A. Touba and Bahram Pouya; “Testing Embedded Cores Using Partial Isolation Rings”; 1997 IEEE, pp. 10-16.

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