Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2001-08-22
2003-09-09
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S683000, C257S684000, C257S676000, C257S678000, C257S698000, C257S777000, C257S779000, C257S780000, C257S781000, C257S782000, C257S785000, C257S786000, C257S691000, C257S787000, C438S112000, C438S124000, C438S125000, C438S126000, C438S127000, C174S260000, C174S261000, C361S767000, C361S777000, C361S783000, C264S017000, C264S272150, C029S025010
Reexamination Certificate
active
06617680
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to chip carriers, semiconductor packages and fabricating methods of the semiconductor packages, and more particularly, to a chip carrier, a semiconductor package and a fabricating method of the semiconductor package, in which electrical static produced on a surface of the semiconductor package is discharged to outside of the semiconductor package.
BACKGROUND OF THE INVENTION
It is desired for semiconductor packages to be provided with I/O connections in higher density, in an effort to improve electrical and operational performance for electronic products. Therefore, a BGA semiconductor package employs a plurality of array-arranged solder balls for electrically connecting a semiconductor chip to external devices, so as to desirably increase the I/O connections for allowing the BGA semiconductor package to be a mainstream product.
Generally, as shown in
FIG. 8
, a BGA semiconductor package
1
substantially comprises a chip carrier
10
having a first side and a second side opposing the first side, a semiconductor chip
40
mounted on the first side of the chip carrier
10
, a plurality of conductive elements
50
such as metallic bonding wires for electrically connecting the semiconductor chip
40
to the chip carrier
10
, an encapsulant
70
formed of a molding compound such as epoxy resin for encapsulating the semiconductor chip
40
and the conductive elements
50
on the first side of the chip carrier
10
; and a plurality of solder balls
80
implanted on the second side of the chip carrier
10
for electrically connecting the semiconductor chip
40
to external devices.
The chip carrier
10
is commonly made of a material such as BT (bismaleimide triazine) resin, and includes a base layer
11
having a first surface and a second surface opposing the first surface. On the first surface of the base layer
11
there are formed a die pad
16
for mounting the semiconductor chip
40
thereon and a plurality of conductive traces
12
electrically connected to the semiconductor chip
40
. On the second surface of the base layer
11
there are disposed a plurality of ball pads
14
for implanting solder balls
80
thereon, while the ball pads
14
are electrically connected to the conductive traces
12
by a plurality of vias
13
formed through the base layer
11
. A solder mask layer
15
is formed on each of the first and second surfaces of the base layer
11
, in a manner that part of the conductive traces
12
electrically connected to the semiconductor chip
40
on the first surface and the ball pads
14
on the second surface are respectively expose to outside of the solder mask layer
15
, so as to prevent the conductive traces
12
from coming into contact with one another for eliminating the occurrence of short circuit, and protect the conductive traces
12
against external detrimental factors.
The BGA semiconductor package
1
is fabricated by the steps as follows: preparing a chip carrier as the one described above; performing a die bonding process for mounting at least one semiconductor chip on a die pad formed on a first side of the chip carrier; providing a plurality of conductive elements for electrically connecting the semiconductor chip to the chip carrier; performing a molding process for forming an encapsulant, which encapsulated the semiconductor chip and the conductive elements on the first side of the chip carrier; performing a de-molding process for ejecting the semi-fabricated semiconductor package form a mold used in the molding process by eject pins formed on the mold; performing a ball implanting process for implanting a plurality of solder balls on ball pads formed on a second side of the chip carrier; and performing a singulating process for forming individual fabricated semiconductor packages.
U.S. Pat. No. 5,450,283 discloses a mold
100
, which can be used in the foregoing molding and de-molding processes, as shown in FIG.
4
. The mold
100
includes a top mold
110
and a bottom mold
120
engaged with the top mold
110
, wherein plurality of eject pins
111
,
121
respectively hang bias means
112
,
122
such as spiral springs are formed on the top and bottom molds
110
,
120
. Further, on an engaged surface of the top mold
110
there is formed a molding cavity
113
, while on an engaged surface of the bottom mold
120
there is formed a plurality of pilot pins
123
for positioning a chip carrier.
FIGS. 4A-4D
illustrate the steps involved in using the conventional mold
100
in the foregoing molding and de-molding processes. After completing the die bonding and electrically connecting processes, the semi-fabricated semiconductor package
1
A is horizontally placed on the engaged surface of the bottom mold
120
, in a manner that a plurality of pilot holes
18
preformed on the chip carrier
10
are coupled to the pilot pins
123
of the bottom mold
120
, for positioning the chip carrier
10
on the engaged surface of the bottom mold
120
. Then, the top mold
110
is engaged with the bottom mold
120
for performing the molding process, so as to form the encapsulant
70
for encapsulating the semiconductor chip and the conductive elements on the first side of the chip carrier
10
, as shown in FIG.
4
B.
Then, the de-molding process is performed for ejecting the semiconductor package
1
A from the mold
100
. As shown in
FIG. 4C
, first, the top mold
110
is moved upwardly, so as to eject the semi-fabricated semiconductor package IA after molding from the molding cavity
113
of the top bottom
110
by resilient force of the bias means
112
, while the eject pins
111
of the top mold
110
are maintained in position, and the semi-fabricated semiconductor package IA are retained on the engaged surface of the bottom mold
120
Moreover, as shown in
FIG. 4D
, the bottom mold
120
is moved downwardly to an end position, where the eject pins
121
counteract bias force of the bias means
122
and protrude from the engaged surface of the bottom mold
120
, so as to eject the semi-fabricated semiconductor package
10
A from the engaged surface of the bottom mold
120
, and remove the semi-fabricated semiconductor package IA from the mold
100
.
In the molding process, a molding compound used for forming the encapsulant
70
is injected to the molding cavity
113
of the mold
100
, and a large amount of electrical static is produced due to friction between mold flow of the molding compound and a solder mask layer
15
on the chip carrier
10
disposed on the engaged surface of the bottom mold
120
. Similarly, in the de-molding process, electrical static is also generated at a great amount during ejecting the semi-fabricated semiconductor package
1
A from the mold
100
. However, as the solder mask layer
15
on the chip carrier
10
and the encapsulant
70
are both made of electrical insulative materials, the electrical static can not be transmitted therethrough to the mold
100
to be discharged to outside of the mold
100
. Therefore, the electrical static is retained on the semiconductor chip, the conductive elements or the conductive traces of the semi-fabricated semiconductor package
1
A. This seriously damages the package, and tends to cause electrical leakage, as well as deteriorates the quality of the package.
Accordingly, U.S. Pat. No. 6,214,645 discloses a mold and a chip carrier for preventing electrical static from being retained therein, as shown in
FIGS. 5-7
. In a first embodiment of the chip carrier, besides a solder mask layer
15
, on a second side of the chip carrier
10
disposed on an engaged surface of a bottom mold
120
there is formed a metallic protrusion
20
to be used as a grounding means, for being electrically connected to the engaged surface of the bottom mold
120
, so as to allow the electrical static to be discharged through the metallic protrusion
20
and the bottom mold
120
to the outside in a molding process, as shown in FIG.
5
.
In a second embodiment of the chip carrier, as shown in
FIG. 6
, on an inside wall of a pilot hole
18
disposed in
Chien-Chih Chen
Lai Chin-Wen
Lai Yu-Ting
Clark Sheila V.
Corless Peter F.
Edwards & Angell LLP
Jensen Steven M.
Ortiz Edgardo
LandOfFree
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