Chip carrier for accommodating passive component

Details Chip carrier for accommodating passive component Chip carrier for accommodating passive component

2002-01-02

2003-02-18

Lam, Cathy (Department: 1725)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S779000, C257S783000, C257S787000, C174S050510, C174S255000, C174S258000

Reexamination Certificate

active

06521997

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to chip carriers, and more particularly, to a chip carrier for accommodating chips and passive components that are electrically connected to the chip carrier.
BACKGROUND OF THE INVENTION
In accomplishment with desirable electricity and functionality, it tends to incorporate passive components such as capacitor, resistor, or inductor in a semiconductor package.
FIG. 5A
illustrates bonding between a passive component and solder pads on a substrate. The substrate
70
is formed at predetermined positions with a pair of solder pads
71
that are properly spaced apart and respectively exposed to outside of a solder mask layer
72
covering the substrate
70
. After a proper amount of solder paste
73
is applied on the solder pads
71
, it is ready to adhere two ends
740
of a passive component
74
to the solder paste
73
. Then, a reflow soldering process is performed for allowing the passive component
74
to be electrically connected to the solder pads
71
by the solder paste
73
.
However, the applied amount of solder paste
73
and height of the solder paste
73
after being reflow soldered are difficult to be precisely controlled, and the solder mask layer
72
is hardly achieved with perfect surface flatness; when the solder mask layer
72
is made uneven, the passive component
74
mounted on the soldered solder paste
73
cannot closely abut against the solder mask layer
72
, with a gap
75
, mostly 10 to 30 &mgr;m in height, being undesirably left between the passive component
74
and the solder mask layer
72
. Such a gap
75
is dimensionally smaller than fillers contained in an encapsulating resin used for forming an encapsulant
76
that encapsulates the passive component
74
. Therefore, during a molding process, the encapsulating resin is not permeable to fill the tiny gap
75
, making the passive component
74
undesirably spaced with the solder mask layer
72
by the gap
75
, after the encapsulant
76
is formed by molding. In subsequent processes such as solder ball implantation or surface mounting processing, the solder paste
73
is softened under a high temperature condition, and the softened solder paste
73
on the two solder pads
71
may bridge with each other through the gap
75
by virtue of capillary effect, as shown in FIG.
5
B. Once the solder paste
73
is bridged, it results in short circuit of the passive component
74
, and thus undesirably deteriorates the quality and yield of fabricated products.
U.S. Pat. No. 5,311,405 entitled “Method and Apparatus for Aligning and Attaching a Surface Mount Component”, discloses a method for positionally aligning a passive component mounted on a substrate; however, problems caused by the existence of a gap formed between the passive component and the substrate, still cannot be solved.
In another semiconductor package with a passive component being mounted on a substrate, the passive component is not enclosed by an encapsulant used for chip encapsulation, but an electrically-insulative resin is applied for entirely coating the passive component prior to wire bonding and molding processes. Since the passive component on the substrate interferes in position with gold wires used for electrically connecting a chip to the substrate, it is necessary to pre-encapsulate the passive component before forming the gold wires, so as to prevent the gold wires from coming into contact with the naked passive component due to component shifting or wire sagging in subsequent processes. If the gold wires occur to touch the naked passive component, short circuit is induced. Therefore, with the passive component being enclosed by the insulative resin, even if the gold wires are sagged in position, the insulative resin protects the passive component from being in direct contact with the gold wires, so that short circuit can be prevented from occurrence. However, this conventional semiconductor package is still defective for incapable of effectively filling a gap between the passive component and the substrate with the insulative resin, thereby easily causing the passive component being short-circuited due to bridging of solder paste used for attaching the passive component onto the substrate, as mentioned above.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a chip carrier for accommodating a passive component, which can effectively prevent the occurrence of short circuit between the passive component and solder pads.
In accordance with the above and other objectives, the present invention proposes a chip carrier for accommodating a passive component, comprising: a core layer defined with a chip attach area for mounting at least a chip thereon, and a trace forming area surrounding the chip attach area, for forming a plurality of conductive traces on the trace forming area; a solder mask layer applied onto the trace forming area; and at least a pair of spaced-apart solder pads formed on the trace forming area and partly exposed to outside of the solder mask layer, wherein a recessed portion is formed at the solder mask layer between the pair of the solder pads, allowing a bottom surface of a passive component that is bonded by solder paste to the solder pads, to form a passage in association with the recessed portion, and the passage is sufficiently dimensioned for allowing a resin material used in encapsulation of the passive component to pass through the passage.
The recessed portion of the solder mask layer can be made as rectangular, circular or elliptic shape without being particularly limited, and is preferably dimensioned not to interfere with routing of the conductive traces.


REFERENCES:
patent: 5311405 (1994-05-01), Tribbey et al.
patent: 6150193 (2000-11-01), Glenn
patent: 6177731 (2001-01-01), Ishida et al.
patent: 6228466 (2001-05-01), Tsukada et al.
patent: 6245594 (2001-06-01), Wu et al.
patent: 6294840 (2001-09-01), McCormick
patent: 6388335 (2002-05-01), Lam
patent: 6448644 (2002-09-01), Lin

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