Chip card circuit with monitored access to a test mode

Details Chip card circuit with monitored access to a test mode Chip card circuit with monitored access to a test mode

2005-08-23

2005-08-23

Le, Don (Department: 2819)

Electronic digital logic circuitry

Security

C326S038000, C327S525000

Reexamination Certificate

active

06933742

ABSTRACT:
A circuit for monitoring an entry into a test mode of a chip circuit has a fusible link which can be fired via a firing transistor. A flipflop, which permits access to the test mode, is set by a resulting voltage drop, with the aid of an edge detector. The number of times the test mode has been accessed can be detected from the number of fired fusible links.

REFERENCES:
patent: 5305267 (1994-04-01), Haraguchi et al.
patent: 5617366 (1997-04-01), Yoo
patent: 6121820 (2000-09-01), Shishikura
patent: RE36952 (2000-11-01), Zagar et al.
patent: 6281739 (2001-08-01), Matsui
patent: 6353336 (2002-03-01), Lindley et al.
patent: 6628144 (2003-09-01), Loughmiller et al.
patent: 6686790 (2004-02-01), Cutter et al.

Affiliated with

Also associated with

Rating

Chip card circuit with monitored access to a test mode does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip card circuit with monitored access to a test mode, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip card circuit with monitored access to a test mode will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3441785