Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1999-09-27
2001-08-07
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S695000, C216S088000
Reexamination Certificate
active
06271138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to methods for forming planarized layers within microelectronics fabrications. More particularly, the present invention relates to chemical mechanical polish (CMP) planarizing methods for forming planarized layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and microelectronic device and patterned microelectronic conductor layer dimensions have decreased, it has become more common within the art of microelectronic fabrication to employ within microelectronic fabrications multiple vertically disposed patterned microelectronic conductor layers within a microelectronic fabrication in order to provide for greater functionality within the microelectronic fabrication.
While the use within microelectronic fabrications of increased numbers of vertically disposed patterned microelectronic conductor layers will certainly continue in order to provide microelectronic fabrications with increased levels of microelectronic fabrication functionality, microelectronic fabrications are typically not fabricated with increasing numbers of vertically disposed patterned microelectronic conductor layers entirely without problems. In that regard, it is often required when forming microelectronic fabrications with increased numbers of vertically disposed patterned microelectronic conductor layers to employ when forming either or both of: (1) the vertically disposed patterned microelectronic conductor layers; or (2) dielectric layers which separate the vertically disposed patterned microelectronic conductor layers, planarizing methods which provide either or both of those layers with nominally planar surfaces in order to assure that microelectronic fabrications within which are formed the patterned microelectronic conductor layers are formed with acceptable levels of functionality and reliability.
To provide microelectronics layers, including microelectronics conductor layers, microelectronics semiconductor layers and microelectronics dielectric layers, with nominally planar surfaces, it common in the art of microelectronics fabrication to employ planarizing methods such as but not limited to reactive ion etch (RIE) etchback planarizing methods and chemical mechanical polish (CMP) planarizing methods. While chemical mechanical polish (CMP) planarizing methods are in particular desirable within the art of microelectronic fabrication for fabricating microelectronic layers with enhanced planarity, chemical mechanical polish (CMP) planarizing methods are also not entirely without problems within the art of microelectronic fabrication insofar as chemical mechanical polish (CMP) planarizing methods do not always provide an optimally planar surface of a chemical mechanical polish planarized layer within a microelectronic fabrication.
It is thus towards the goal of providing within microelectronic fabrications chemical mechanical polish (CMP) planarized microelectronic layers within enhanced planarity that the present invention is directed.
Various apparatus and methods have been disclosed in the art of microelectronic fabrication for forming planarized layers with desirable properties within microelectronic fabrications.
For example, Schultz, et al., in U.S. Pat. No. 5,234,867, discloses a chemical mechanical polish (CMP) planarizing apparatus and an associated chemical mechanical polish (CMP) planarizing method for chemical mechanical polish (CMP) planarizing a semiconductor substrate with greater uniformity. To realize that object, the chemical mechanical polish (CMP) planarizing apparatus and the chemical mechanical polish (CMP) planarizing method employ a rotating non-circular chemical mechanical polish (CMP) planarizing pad juxtaposed a rotating semiconductor substrate, where at least a portion of the rotating semiconductor substrate is moved beyond an edge of the rotating non-circular chemical mechanical polish (CMP) planarizing pad when chemical mechanical polish (CMP) planarizing the semiconductor substrate.
In addition, Jairath, in U.S. Pat. No. 5,665,656, discloses a chemical mechanical polish (CMP) planarizing apparatus and an associated chemical mechanical polish (CMP) planarizing method for chemical mechanical polish (CMP) planarizing a semiconductor substrate with enhanced uniformity, reduced materials consumption and reduced chemical mechanical polish (CMP) planarizing apparatus size. To realize the foregoing objects, the chemical mechanical polish (CMP) planarizing apparatus and the chemical mechanical polish (CMP) planarizing method employ a rotating semiconductor substrate which is contacted by a lateral edge of a rotating conical polishing pad rather than a planar surface of a rotating planar polishing pad.
Finally, Huang, in U.S. Pat. No. 5,679,211, discloses a reactive ion etch (RIE) etchback planarizing method for forming with enhanced etchback uniformity a reactive ion etch (RIE) etchback planarized spin-on-glass (SOG) planarizing layer within a semiconductor integrated circuit microelectronics fabrication. To realize the foregoing object, the reactive ion etch (RIE) etchback planarizing method employs: (1) a series of sequential and repetitive partial reactive ion etch (RIE) etchback planarizings of the spin-on-glass (SOG) planarizing layer while employing a fluorocarbon containing plasma which forms a series of polymer residue layers upon a corresponding series of partially reactive ion etch (RIE) etchback planarized spin-on-glass (SOG) planarizing layers; followed by (2) an intervening series of sequential and repetitive strippings of the series of polymer residue layers while employing an oxygen containing plasma.
Desirable in the art of microelectronic fabrication are additional chemical mechanical polish (CMP) planarizing methods which may be employed within microelectronic fabrications to provide within microelectronic fabrications chemical mechanical polish (CMP) planarized microelectronic layers within enhanced planarity.
It is towards the foregoing object that the present invention that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized microelectronic layer within a microelectronic fabrication.
A second object of the present invention is to provide a chemical mechanical polish (CMP) planarizing method in accord with the first object of the present invention, where the chemical mechanical polish (CMP) planarized microelectronic layer is formed with enhanced planarity.
A third object of the present invention is to provide a chemical mechanical polish (CMP) planarizing method in accord with the first object of the present invention and the second object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized microelectronic layer within a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a microelectronic layer. There is then planarized, while employing a chemical mechanical polish (CMP) planarizing method, the microelectronic layer to form a chemical mechanical polish (CMP) planarized microelectronic layer. Within the method of the present invention, the microelectronic layer when formed over the substrate is formed with a thickness variation which compensates for a chemical mechanical polish (CMP) rate non-uniformity when forming while employing the chemical mechanical polish (CMP) planarizing method the
Chang Weng
Jang Syun-Ming
Ackerman Stephen B.
Deo Duy-Vu
Saile George O.
Stanton Stephen G.
Taiwan Semiconductor Manufacturing Company
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