Check instruction and method

Details Check instruction and method Check instruction and method

1999-12-15

2003-01-28

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Specialized instruction processing in support of testing,...

C714S035000

Reexamination Certificate

active

06513110

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to digital computers, and, more particularly, to a software technique for verifying that execution of an instruction will not produce an unrecoverable processor error.
BACKGROUND
Processors function by executing instructions. Sometimes an instruction cannot be carried out for any of a variety of possible reasons and generates an exception. For example, a memory page at which an instruction resides may not be in main memory and must be paged in before the instruction can execute, or an instruction might not have permission to store to a specific address. When such an exception occurs, further processing of the instruction is temporarily halted, until the exception is resolved. Resolution is accomplished with an exception handler, a software routine specifically designed to deal with such exceptions. A processor typically contains different exception handlers to handle each kind of exception that might occur. Typically those software routines handle and resolve the exception before further processing of program instructions is permitted to continue.
Whenever a host instruction is to be executed, numerous checks (herein referred to as “preliminary checks”) are routinely made at execution units of the processor to determine whether the instruction will be executed or, alternately, cause an exception. As an example, a store operation is performed by a write of data to an address in the memory (the hardware unit) of the processor. Before allowing the write to proceed, the memory checks for write permissions and for page present.
Other checks of that instruction (herein referred to as “final checks”), not material to the invention, are also made by the hardware unit to which the operation performed is directed after the result of the operation has been committed. That check (or checks) could also result in an exception. As example during the write of data by the processor into the memory unit, an electronic “glitch”, though rare, may occur and corrupt the data being written. The memory unit detects the corruption of data and signals the processor of the damaged data. However since the write operation was committed, the written data remains corrupted, creating an error. The invention does not offer a solution to that kind of problem.
If the instruction passes the preliminary checks, the operation specified in the instruction is completed. If any fail, an exception occurs. The processor is then required to resolve the exception before the operation specified in the instruction, the final effect, the write to memory in the preceding example, can be performed.
The foregoing is understood to apply to processors in general and to those processors that process very long instruction word (VLIW) instructions. One example of a VLIW processor disclosed in the patent literature is found in U.S. Pat. No. 5,832,205 to Kelly et al, granted Nov. 3, 1998, entitled, Memory Controller For A Microprocessor For Detecting A Failure of Speculation On The Physical Nature of A Component Being Addressed, assigned to Transmeta Corporation (referred to as the '205 Transmeta patent), the disclosure of which is incorporated herein by reference. Another appears the improved VLIW processor system of Torvalds and Keppel based on the foregoing invention of the '205 Transmeta patent presented in a copending application Ser. No. 09/417358, filed Oct. 13, 1999, entitled Controlling Instruction Translation Using Dynamic Feedback, (herein referred to as the “improved Transmeta computer”), assigned to Transmeta Corporation, the disclosure of which is incorporated herein by reference. As later herein described in greater detail, the present invention has particular application to and improves the operation of the foregoing computers. However, although the present invention has application to the improved Transmeta computer, it should be understood that the invention may also be found to benefit other types of computers as well.
The microprocessor of the '205 Transmeta patent is formed by a combination of a hardware processing portion (called a “morph host”), and an emulating software portion, referred to therein as “code morphing software”. Among other things, the code morphing software carries out a significant portion of the functions of processors in software, reducing the hardware required for processing and the greater electrical power that such hardware requires. The '205 Transmeta computer serves as the host system capable of executing software programs designed with an instruction set intended to run on a computer system of different design, the target system, one, such as the X86 type processor, that contains an instruction set unique to the target system, but foreign to the host system.
The present invention addresses the preliminary checks and the exceptions that may result therefrom (the latter herein referred to as a preliminary exception), not the final checks or any exceptions that result from the latter (herein called a final exception, to distinguish from the former exception). Thus, as used herein in connection with the invention, the term preliminary exception refers to a particular kind of out-of-ordinary event that occurs before the operation defined in the instruction is committed; and differs from the other exceptions as may result from the hardware check by that hardware unit of the processor upon actually performing the operation.
Any operation may require preliminary checks. Those checks must execute and generate any needed exceptions before the results of the operation are committed to the machine state. In many prior processors the preliminary checks are performed by the hardware and so are invisible to the software programmer. The hardware may perform the checks before the operation by the hardware, or, in a processor that employs out-of-order execution, may perform the checks concurrently with or even after the bulk of the operation, provided that, with the latter two techniques, the check completes before the operation result is committed.
In the processor of the improved Transmeta computer and in other processors that support speculation, software-managed hardware controls the committing of most machine state. Therefore, with processors of the foregoing type, it is sufficient to speculatively execute the desired operation, provided that the check is executed before the final commit of the result to the machine state.
Some operations, however, may not be speculated. For example, a read of an external device may cause the state of the device to change. The processor of the improved Transmeta computer is unable to roll-back or undo such a read operation. Hence, in the case of the read of an external device, the preliminary check must always precede the read operation. Any failure to perform the preliminary check could potentially result in an unrecoverable error.
In addition, it may sometimes be advantageous to perform the preliminary check as early as possible, so that an exception, as may be generated thereby, may be handled immediately, instead of executing speculated operations and then discarding the result upon occurrence of such exception.
One example of the manner in which preliminary checking is used is a read-modify-write operation, an operation used to increment a register of a peripheral device, external to the processor. Typically, load operations contain implied tests, such as “Readable”, and write operations have tests, such as “Writeable”. For the read-modify-write to execute correctly, either both the read and the write must occur, or neither should occur. It is an unrecoverable error if only the read occurs. However, an ordinary “load, increment and store” sequence may successfully execute the load, and then fail on the store, as could occur, as an example, if the location is readable, but is not writeable.
As an advantage, the present invention is available for use by the software engineer when a program is being authored, and allows the software engineer to integrate checks within that program. The chec

Affiliated with

Also associated with

Rating

Check instruction and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Check instruction and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Check instruction and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3029300