Check bit free error correction for sleep mode data retention

Details Check bit free error correction for sleep mode data retention Check bit free error correction for sleep mode data retention

2007-01-30

2007-01-30

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S754000

Reexamination Certificate

active

10066497

ABSTRACT:
A DRAM memory has a reduced refresh rate in a sleep mode to conserve power. Error Correction Codes (ECC) are used to correct errors that may arise due to the reduced refresh rate. ECC encoding occurs at the time of entering the sleep mode and ECC decoding for error detection and correction need only take place upon wake up when resuming active mode. In addition, the memory system reassigns a portion of the memory for storing the additional parity bits required for the error correcting code (ECC).

REFERENCES:
patent: 4933940 (1990-06-01), Walter et al.
patent: 4935900 (1990-06-01), Ohsawa
patent: 5465367 (1995-11-01), Reddy et al.
patent: 6199139 (2001-03-01), Katayama et al.
patent: 6697992 (2004-02-01), Ito et al.

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