Charging circuit and semiconductor memory device using the same

Details Charging circuit and semiconductor memory device using the same Charging circuit and semiconductor memory device using the same

2002-06-24

2004-04-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189070, C365S189090, C365S193000, C365S194000, C365S233100, C365S233500

Reexamination Certificate

active

06717872

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a charging circuit and a semiconductor memory device using the charging circuit, and in particular, to a charging circuit for charging a load circuit to a prescribed voltage level, and a semiconductor memory device for charging a bit line using the charging circuit.
2. Description of the Related Art
A semiconductor memory device includes a plurality of memory cells arranged in a matrix. Before reading information stored in one of the memory cells or writing information to one of the memory cells, a bit line connected to the memory cell needs to be charged. In the case of a nonvolatile semiconductor memory device, the charging operation is performed in order to raise the speed of reading the information from the memory cell. In the case of a volatile semiconductor memory device, the charging operation is performed in order to prevent inadvertent overwriting of the information stored in the memory cell when reading the information.
FIG. 7
shows an exemplary charging circuit
700
which is conventionally and generally used in a single bit semiconductor memory device. The charging circuit
700
includes three N-type MOS transistors N
0
, N
1
and N
2
. A drain of the N-type MOS transistor N
1
is connected to a power supply VCC via a resistor R
1
, and a source of the N-type MOS transistor N
1
is connected to ground VSS. A gate of the N-type MOS transistor N
1
is connected to a source of the N-type MOS transistor N
2
. A gate of the N-type MOS transistor N
2
is connected to a node
23
between the drain of the N-type MOS transistor N
1
and the resistor R
1
. A drain of the N-type MOS transistor N
2
is connected to the power supply VCC. The gate of the N-type MOS transistor N
2
is connected to a gate of the N-type MOS transistor N
0
, and the source of the N-type MOS transistor N
2
is connected to a source of the N-type MOS transistor N
0
. The source of the N-type MOS transistor N
0
is also connected to an output node VPR, which is an output terminal of the charging circuit
700
. A drain of the N-type MOS transistor N
0
is connected to the power supply VCC via a resistor R
0
. A node
22
between the drain of the N-type MOS transistor N
0
and the resistor R
0
is connected to a sense amplifier (not shown).
In the charging circuit
700
, a load circuit to be charged (not shown) is connected to the output node VPR. The node
22
connected to the drain of the N-type MOS transistor N
0
conveys a change in the level of the charging current, which is output from the output node VPR, to the sense amplifier as a change in the voltage. An inverter, including the N-type MOS transistor N
1
and the resistor R
1
, detects the voltage level of the output node VPR from the gate of the N-type MOS transistor N
1
. Then, the inverter feeds back the voltage level of the output node VPR via the node
23
, connected to the drain of the N-type MOS transistor N
1
, to the gate of the N-type MOS transistor N
2
and to the gate of the N-type MOS transistor N
0
. Thus, the charging operation performed via the output node VPR and the operation of the sense amplifier are improved in speed.
FIG. 8
shows an exemplary charging circuit used for a semiconductor memory device including a pair of complementary bit lines (a bit line BIT and a bit line /BIT having a logic level inverted from the logic level of the bit line BIT). In
FIG. 8
, a power supply VM is a power supply or an output terminal of an internal voltage drop circuit.
The charging circuit
800
includes an N-type MOS transistor N
3
between the power supply VM and the bit line BIT and an N-type MOS transistor N
4
between the power supply VM and the bit line /BIT. The N-type MOS transistors N
3
and N
4
are load transistors. An N-type MOS transistor NEQ for equalizing the bit lines is provided between the bit lines BIT and /BIT (i.e., for charging the bit lines BIT and /BIT to an equal potential). In the case where a with stand voltage of the memory cell (not shown) connected to the bit lines BIT and /BIT is lower than the external supply voltage, the output terminal of the internal voltage drop circuit is used as the power supply VM.
Drains of the N-type MOS transistor N
3
and N
4
are connected to the power supply VM. A source of the N-type MOS transistor N
3
is connected to the bit line BIT, and a source of the N-type MOS transistor N
4
is connected to the bit line /BIT. Gates of the N-type MOS transistors N
3
and N
4
are connected to each other. A drain and a source of the N-type MOS transistor NEQ are respectively connected to the source of the N-type MOS transistor N
3
and the source of the N-type MOS transistor N
4
. A gate of the N-type MOS transistor NEQ is connected to the gates of the N-type MOS transistors N
3
and N
4
.
The N-type MOS transistor NEQ is connected to the bit lines BIT and /BIT so as to equalize the bit lines BIT and /BIT. The gate of the N-type MOS transistor NEQ receives an equalizing signal EQ
1
. The equalizing signal EQ
1
is also input to the gates of the N-type MOS transistors N
3
and N
4
.
While the equalizing signal EQ
1
is at a HIGH logic level, the N-type MOS transistors N
3
, N
4
and NEQ are all in an ON state. The source and the drain of the N-type MOS transistor N
3
are conductive with each other, and the source and the drain of the N-type MOS transistor N
4
are conductive with each other. Therefore, the voltage of the power supply VM is applied to the bit lines BIT and /BIT. Since the drain and the source of the N-type MOS transistor NEQ are also conductive with each other, the equalization operation is performed for charging the bit lines BIT and /BIT to an equal potential.
As a result, while the equalizing signal EQ
1
is at a HIGH logic level, the voltage of the power supply VM is supplied to the memory connected to the bit lines BIT and /BIT.
As described above, the charging circuit
800
uses N-type MOS transistors. The threshold voltage drop function of the N-type MOS transistors is utilized to pre-charge the bit lines BIT and /BIT to ½ VCC. This provides the effect of reducing power consumption and noise while charging and discharging the bit lines BIT and /BIT.
A conventional single bit semiconductor memory device uses the charging circuit
700
shown in
FIG. 7
so as to charge the bit line utilizing a voltage drop corresponding to the threshold voltage Vth of the N-type MOS transistors. A semiconductor memory device integrally including an internal voltage drop circuit uses the charging circuit
800
shown in FIG.
8
. The complementary bit lines BIT and /BIT connected to all the memory cells are charged, using the voltage of the output terminal VM of the internal voltage drop circuit as the power supply voltage of the N-type MOS transistors.
The charging circuit
700
has the following problem. As the potential of the sources of the N-type MOS transistors increases during the charging operation, the difference in potential between the gate and the source of each N-type MOS transistor is reduced. This is accompanied by reduction in the driving capability of the N-type MOS transistors, which inevitably increases the charging time period.
The charging circuit
800
has the following problem. The load on the internal voltage drop circuit for supplying a voltage for charging is excessively high. Accordingly, an excessively large output capacity is required in order to obtain stable operation.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a charging circuit for charging a prescribed load circuit to a prescribed potential includes a charging driving circuit connected to the load circuit for supplying a charging signal to the load circuit from an output end of the charging driving circuit; a time constant circuit for receiving the charging signal, changing a time constant of the charging signal and outputting a transition signal having a prescribed transition time period; a control circuit for outputting a control signal for setting a time constant of the time const

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