Charge-trapping memory device and methods for operating and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S216000, C438S263000, C438S591000, C438S201000

Reexamination Certificate

active

07402490

ABSTRACT:
To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

REFERENCES:
patent: 5768192 (1998-06-01), Eitan
patent: 6011725 (2000-01-01), Eitan
patent: 6324099 (2001-11-01), Iijima
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6627498 (2003-09-01), Willer et al.
patent: 6639271 (2003-10-01), Zheng et al.
patent: 6673677 (2004-01-01), Hofmann et al.
patent: 6806517 (2004-10-01), Kim et al.
patent: 2003/0080372 (2003-05-01), Mikolajick
patent: 2003/0134475 (2003-07-01), Hofmann et al.
patent: 2003/0148582 (2003-08-01), Willer et al.
patent: 2003/0161192 (2003-08-01), Kobayashi et al.
patent: 2003/0185055 (2003-10-01), Yeh et al.
patent: 2004/0097037 (2004-05-01), Hofmann et al.
patent: 101 44 700 (2002-04-01), None
patent: 100 36 911 (2002-06-01), None
patent: 1 103 980 (2001-05-01), None
patent: WO 02/11145 (2002-02-01), None
patent: WO 2004/053982 (2004-06-01), None
Yeh, C.C., et al., “PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory,” IEEE 2002, 4 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Charge-trapping memory device and methods for operating and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Charge-trapping memory device and methods for operating and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Charge-trapping memory device and methods for operating and... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2763624

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.