Charge-trapping memory device and method of production

Details Charge-trapping memory device and method of production Charge-trapping memory device and method of production

2006-11-07

2006-11-07

Malsawma, Lex H. (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

07132337

ABSTRACT:
Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

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