Charge-trapping memory cell array and method for production

Details Charge-trapping memory cell array and method for production Charge-trapping memory cell array and method for production

2005-12-06

2005-12-06

Huynh, Andy (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S257000, C438S263000, C438S264000, C438S591000, C438S593000, C257S314000, C257S315000, C257S316000, C257S324000, C257S326000

Reexamination Certificate

active

06972226

ABSTRACT:
In a memory cell array comprising charge-trapping memory cells, local interconnects along the direction of the wordlines for connecting source/drain regions of adjacent memory cells to bitlines are formed by selective deposition of silicon or polysilicon bridges at sidewalls of the semiconductor material within upper recesses in the dielectric material of shallow trench isolations running across the wordlines.

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patent: WO 2004/053982 (2004-06-01), None

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