Charge trap memory with avalanche generation inducing layer

Details Charge trap memory with avalanche generation inducing layer Charge trap memory with avalanche generation inducing layer

2006-02-03

2009-11-10

Phung, Anh (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE29309

Reexamination Certificate

active

07615821

ABSTRACT:
The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the active region appropriately, and it is a difference from the conventional art. The present invention induces electrons to band-to-band tunnel at the PN junction with the source/drain region by the multi-doped layers, and accelerates the electrons at the reverse bias to generate an avalanche phenomenon. Therefore, the method for operating a memory array of the present invention comprises programming by injecting holes which are generated by the avalanche phenomenon into multi-dielectric layers of each memory cells, and erasing by injecting electrons through an F-N tunneling from channels into the multi-dielectric layers of each memory cells.

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