Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-14
2001-02-13
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000
Reexamination Certificate
active
06187635
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to semiconductor devices and, more particularly, to a memory devices such as EPROMs and Flash EPROMs and, even more particularly, to a channel hot electron (CHE) programmed memory device having improved reliability and operability.
BACKGROUND OF THE INVENTION
CHE programming of electrically erasable programmable read-only memories (EPROMs) and flash (EPROMs) can generate between 50 &mgr;A-100 &mgr;A of cell current. For state of the art devices, which are often built onto P-type epitaxial layers over a low resistivity substrate, this substrate current sinks into the low resistivity layer and does not generate significant voltage drop. However, for EPROMs and flash EPROMs that use a non-epitaxial layer substrate, or ones that are built on an isolated P-well surrounded by a deep N-well, such as in a triple well process, the substrate current that is generated during programming can build up large voltage drops across the resistive FAMOS P-well region.
If voltage drop exceeds the diode turn-on voltage of approximately 0.7 volts, then the source junction will forward bias. This problem of the resistive P-well situation may be seen in a lowering of the floating-gate avalanche-injection metal oxide semiconductor (FAMOS) BVCEO voltage value. Lowering the BVCEO values, unfortunately, reduces the maximum drain potential of the device. For a constant current programming load line, this reduces the gate current and degrades programmability of the EPROM or flash EPROM.
FIGS. 1 and 2
show the adverse effects of lower and BVCEO voltage values. In particular,
FIG. 1
illustrates a plot of two BVCEO characteristic lines for a flash EPROM cell built over a triple well structure that includes an isolated P-well within a deep N-well. In the first case of line
10
, the isolated P-well is well grounded and the deep N-well potential is at ground potential. The resistance R equals 15 &OHgr;. In the second case of line
12
, the isolated P-well is simulated to be resistive at a value of 15 K&OHgr;. Line
10
shows the shift in the BVCEO characteristic that yields a lowered programming voltage and generally degrades performance of the memory.
Another problem that arises when the substrate current builds up a voltage drop across the resistive FAMOS P-well is that once the source junction forward biases, it sprays electrons into the substrate. Some of the electrons will be collected by the drain junctions of the adjacent cells in the bit line stress mode. In this case, electrons entering the high electric field region near the drain create hot electron-holes pairs. Due to the polarity of the gate field near the drain, these hot electron-hole pairs are likely to be injected into the gate oxide and cause charge loss from the floating gate.
The table of
FIG. 2
shows the effect of rising body potential on bit line stress. In the table of
FIG. 2
, the gate voltage, V
g
, equals zero; the drain voltage, V
d
, equals six volts; and the source voltage, V
s
, equals zero. Bit line stress occurs for approximately one second, in this example. The parameter, V
b
, represents the bins voltage across the resistive FAMOS P-well region. As the
FIG. 2
table shows, with V
b
exceeding 0.7 volts, the threshold voltage, V
t
values of 0.10, 0.05, and 0.5 when V
b
was at or below 0.7 volts. The lowered V
t
, therefore, indicates the degraded programmability that breakdown of the source junction diode causes. Basically, as the substrate potential rises, the charge loss from floating gate rises correspondingly. This phenomenon exhibits an approximately exponential cause and effect relationship. Also, there is some expectation that the above-stated bit line stress mechanism causes grain degradation in flash memory devices as a result of the hot hole injection.
To avoid the above issues, the voltage drop in the substrate during programming should stay below the diode turn on voltage of approximately 0.7 volts. One way to achieve this result is to reduce the FAMOS P-well sheet resistance. Unfortunately, for triple well technology, this solution increases the process complexity. Therefore, there is a desire to build single isolated P-well to meet the CMOS requirements for negative voltage switching, and use the same isolated well for FAMOS devices. In this case, the high sheet resistance of the isolated P-well cannot meet the FAMOS requirements. For large arrays, the substrate bias build-up during programming forward biases the source junction and cause the above-stated device reliability concerns.
Other known solutions to this problem are process-oriented, using either a low-sheet-resistance FAMOS P-well or a very high energy implant. Both solutions, however, increase the process and the device-design complexities.
SUMMARY OF THE INVENTION
In light of the above limitations, there is a need for a CHE programmed memory device having improved reliability and operability that substantially eliminates or reduces problems of forward biasing the isolated P-well junction and emitting electrons into the P-substrate problems, without the undesirable process and device design complexities that affect existing methods and devices.
According to one aspect of the present invention, there is provided a CHE programmed memory device having improved reliability and operability that avoids forward biasing at the isolated P-well junction and emitting electrons into the substrate by slightly forward biasing the deep N-well with respect to the isolated P-well.
In one embodiment of the present invention, the forward bias is applied as a voltage to the deep N-well in the range of −0.3 V-0.5 V, or a negative constant current of approximately −10 &mgr;A) that is pumped into the deep N-well with isolated P-well being grounded. With the isolated P-well/deep N-well diode slightly forward biased, any substrate current generated during programming can easily forward bias this diode more. This results in pumping holes into the P-substrate. In that case, the isolated P-well potential does not rise more than 0.2 V-0.3 V. This essentially eliminates the problems of forward biasing the isolated P-well junction and spraying electrons into the P-substrate.
A technical advantage of the present invention is that is makes the use of resistive isolated P-wells in triple well designs practical by diverting the substrate current into the low resistivity P-substrate during programming. The present invention simplifies the process of building a flash EPROM array over a triple well by eliminating the requirement for a separate low-sheet-resistance, FAMOS P-well, thereby reducing fabrication costs. The present invention does not require an additional well and requires only a small circuit change. Moreover, present the invention is useful for all EPROMs built on triple wells.
REFERENCES:
patent: 5322803 (1994-06-01), Cappelletti et al.
patent: 5712178 (1998-01-01), Cho et al.
patent: 6043123 (2000-03-01), Wang et al.
Booth Richard
Brady III Wade James
Holland Robby T.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Channel hot electron programmed memory device having... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Channel hot electron programmed memory device having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Channel hot electron programmed memory device having... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2593550