Cell structure for dual port SRAM

Details Cell structure for dual port SRAM Cell structure for dual port SRAM

2010-05-04

2011-11-15

Sofocleous, Alexander (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C257S210000, C257S903000, C257SE27098, C257SE27099, C326S119000, C326S121000, C365S230050

Reexamination Certificate

active

08059452

ABSTRACT:
An integrated circuit and methods for laying out the integrated circuit are provided. The integrated circuit includes a first and a second transistor. The first transistor includes a first active region comprising a first source and a first drain; and a first gate electrode over the first active region. The second transistor includes a second active region comprising a second source and a second drain; and a second gate electrode over the second active region and connected to the first gate electrode, wherein the first source and the second source are electrically connected, and the first drain and the second drain are electrically connected.

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Nil, K., et al., “A 90nm Dual-Port SRAM with 2.04μm28T-Thin Cell Using Dynamically-Controlled Column Bias Scheme,” 2004 IEEE International Solid-State Circuits Conference, ISSCC 2004, Session 27, SRAM, 27.9, 10 pages.

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