Cell structure for a semiconductor memory device and method...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S208000, C257S068000, C257S071000, C257SE21658

Reexamination Certificate

active

08084801

ABSTRACT:
In a 6F2cell structure of a memory device and a method of fabricating the same, the plurality of active regions may have a first area at both end portions and a second area at a central portion. A portion of a bit-line contact pad may be positioned on the second area and the other portion may be positioned on a third area of the substrate that may not overlap with the plurality of active regions. The bit line may be connected with the bit-line contact pad at the third area. The cell structure may be more easily formed despite a 6F2-structured unit cell. The plurality of active regions may have an elliptical shape including major and minor axes. The plurality of active regions may be positioned in a major axis direction to thereby form an active row, and may be positioned in a minor axis direction in such a structure that a center of the plurality of active regions is shifted from that of an adjacent active region in a neighboring active row.

REFERENCES:
patent: 2004/0188745 (2004-09-01), Kim et al.
patent: 2005/0186740 (2005-08-01), Kim
patent: 2006/0076599 (2006-04-01), Goo et al.
patent: 272162 (2000-08-01), None
patent: 326811 (2002-02-01), None
patent: 1020030058601 (2003-07-01), None
patent: 1020040008489 (2004-01-01), None
patent: 465632 (2004-12-01), None
patent: 1020050059482 (2005-06-01), None

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